system/watchpoint: Move TCG specific code to accel/tcg/
Keep system/watchpoint.c accelerator-agnostic by moving TCG specific code to accel/tcg/watchpoint.c. Update meson. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240111162032.43378-1-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
16ad9788b5
commit
1c3d42c4c9
@ -24,6 +24,7 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
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specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
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specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
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'cputlb.c',
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'cputlb.c',
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'watchpoint.c',
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))
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))
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system_ss.add(when: ['CONFIG_TCG'], if_true: files(
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system_ss.add(when: ['CONFIG_TCG'], if_true: files(
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143
accel/tcg/watchpoint.c
Normal file
143
accel/tcg/watchpoint.c
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@ -0,0 +1,143 @@
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/*
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* CPU watchpoints
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "qemu/error-report.h"
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#include "exec/exec-all.h"
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#include "exec/translate-all.h"
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#include "sysemu/tcg.h"
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#include "sysemu/replay.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "hw/core/cpu.h"
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/*
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* Return true if this watchpoint address matches the specified
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* access (ie the address range covered by the watchpoint overlaps
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* partially or completely with the address range covered by the
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* access).
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*/
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static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
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vaddr addr, vaddr len)
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{
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/*
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* We know the lengths are non-zero, but a little caution is
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* required to avoid errors in the case where the range ends
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* exactly at the top of the address space and so addr + len
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* wraps round to zero.
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*/
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vaddr wpend = wp->vaddr + wp->len - 1;
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vaddr addrend = addr + len - 1;
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return !(addr > wpend || wp->vaddr > addrend);
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}
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/* Return flags for watchpoints that match addr + prot. */
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int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
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{
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CPUWatchpoint *wp;
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int ret = 0;
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QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
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if (watchpoint_address_matches(wp, addr, len)) {
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ret |= wp->flags;
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}
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}
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return ret;
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}
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/* Generate a debug exception if a watchpoint has been hit. */
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void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
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MemTxAttrs attrs, int flags, uintptr_t ra)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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CPUWatchpoint *wp;
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assert(tcg_enabled());
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if (cpu->watchpoint_hit) {
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/*
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* We re-entered the check after replacing the TB.
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* Now raise the debug interrupt so that it will
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* trigger after the current instruction.
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*/
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bql_lock();
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cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
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bql_unlock();
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return;
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}
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if (cc->tcg_ops->adjust_watchpoint_address) {
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/* this is currently used only by ARM BE32 */
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addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
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}
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assert((flags & ~BP_MEM_ACCESS) == 0);
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QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
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int hit_flags = wp->flags & flags;
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if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
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if (replay_running_debug()) {
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/*
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* replay_breakpoint reads icount.
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* Force recompile to succeed, because icount may
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* be read only at the end of the block.
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*/
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if (!cpu->neg.can_do_io) {
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/* Force execution of one insn next time. */
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cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
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cpu_loop_exit_restore(cpu, ra);
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}
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/*
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* Don't process the watchpoints when we are
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* in a reverse debugging operation.
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*/
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replay_breakpoint();
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return;
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}
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wp->flags |= hit_flags << BP_HIT_SHIFT;
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wp->hitaddr = MAX(addr, wp->vaddr);
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wp->hitattrs = attrs;
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if (wp->flags & BP_CPU
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&& cc->tcg_ops->debug_check_watchpoint
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&& !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
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wp->flags &= ~BP_WATCHPOINT_HIT;
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continue;
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}
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cpu->watchpoint_hit = wp;
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mmap_lock();
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/* This call also restores vCPU state */
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tb_check_watchpoint(cpu, ra);
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if (wp->flags & BP_STOP_BEFORE_ACCESS) {
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cpu->exception_index = EXCP_DEBUG;
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mmap_unlock();
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cpu_loop_exit(cpu);
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} else {
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/* Force execution of one insn next time. */
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cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
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mmap_unlock();
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cpu_loop_exit_noexc(cpu);
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}
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} else {
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wp->flags &= ~BP_WATCHPOINT_HIT;
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}
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}
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}
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@ -18,13 +18,8 @@
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "qemu/error-report.h"
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#include "qemu/error-report.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "exec/translate-all.h"
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#include "sysemu/tcg.h"
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#include "sysemu/replay.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "hw/core/cpu.h"
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#include "hw/core/cpu.h"
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/* Add a watchpoint. */
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/* Add a watchpoint. */
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@ -103,122 +98,3 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
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}
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}
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}
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}
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}
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}
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#ifdef CONFIG_TCG
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/*
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* Return true if this watchpoint address matches the specified
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* access (ie the address range covered by the watchpoint overlaps
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* partially or completely with the address range covered by the
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* access).
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*/
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static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
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vaddr addr, vaddr len)
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{
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/*
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* We know the lengths are non-zero, but a little caution is
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* required to avoid errors in the case where the range ends
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* exactly at the top of the address space and so addr + len
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* wraps round to zero.
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*/
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vaddr wpend = wp->vaddr + wp->len - 1;
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vaddr addrend = addr + len - 1;
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return !(addr > wpend || wp->vaddr > addrend);
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}
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/* Return flags for watchpoints that match addr + prot. */
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int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
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{
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CPUWatchpoint *wp;
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int ret = 0;
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QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
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if (watchpoint_address_matches(wp, addr, len)) {
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ret |= wp->flags;
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}
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}
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return ret;
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}
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/* Generate a debug exception if a watchpoint has been hit. */
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void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
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MemTxAttrs attrs, int flags, uintptr_t ra)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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CPUWatchpoint *wp;
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assert(tcg_enabled());
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if (cpu->watchpoint_hit) {
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/*
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* We re-entered the check after replacing the TB.
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* Now raise the debug interrupt so that it will
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* trigger after the current instruction.
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*/
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bql_lock();
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cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
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bql_unlock();
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return;
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}
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if (cc->tcg_ops->adjust_watchpoint_address) {
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/* this is currently used only by ARM BE32 */
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addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
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}
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assert((flags & ~BP_MEM_ACCESS) == 0);
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QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
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int hit_flags = wp->flags & flags;
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if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
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if (replay_running_debug()) {
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/*
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* replay_breakpoint reads icount.
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* Force recompile to succeed, because icount may
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* be read only at the end of the block.
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*/
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if (!cpu->neg.can_do_io) {
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/* Force execution of one insn next time. */
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cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
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cpu_loop_exit_restore(cpu, ra);
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}
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/*
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* Don't process the watchpoints when we are
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* in a reverse debugging operation.
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*/
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replay_breakpoint();
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return;
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}
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wp->flags |= hit_flags << BP_HIT_SHIFT;
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wp->hitaddr = MAX(addr, wp->vaddr);
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wp->hitattrs = attrs;
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if (wp->flags & BP_CPU
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&& cc->tcg_ops->debug_check_watchpoint
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&& !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
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wp->flags &= ~BP_WATCHPOINT_HIT;
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continue;
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}
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cpu->watchpoint_hit = wp;
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mmap_lock();
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/* This call also restores vCPU state */
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tb_check_watchpoint(cpu, ra);
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if (wp->flags & BP_STOP_BEFORE_ACCESS) {
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cpu->exception_index = EXCP_DEBUG;
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mmap_unlock();
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cpu_loop_exit(cpu);
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} else {
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/* Force execution of one insn next time. */
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cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
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mmap_unlock();
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cpu_loop_exit_noexc(cpu);
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}
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} else {
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wp->flags &= ~BP_WATCHPOINT_HIT;
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}
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}
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}
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#endif /* CONFIG_TCG */
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