hw/i2c/aspeed: Add new-registers DMA slave mode RX support
This commit adds support for DMA RX in slave mode while using the new register set in the AST2600 and AST1030. This patch also pretty much assumes packet mode is enabled, I'm not sure if this will work in DMA step mode. This is particularly useful for testing IPMB exchanges between Zephyr and external devices, which requires multi-master I2C support and DMA in the new register mode, because the Zephyr drivers from Aspeed use DMA in the new mode by default. The Zephyr drivers are also using packet mode. The typical sequence of events for receiving data in DMA slave + packet mode is that the Zephyr firmware will configure the slave address register with an address to receive on and configure the bus's function control register to enable master mode and slave mode simultaneously at startup, before any transfers are initiated. RX DMA is enabled in the slave mode command register, and the slave RX DMA buffer address and slave RX DMA buffer length are set. TX DMA is not covered in this patch. When the Aspeed I2C controller receives data from some other I2C master, it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR address counter and decrementing the I2CC_DMA_LEN counter. It will also update the I2CS_DMA_LEN RX_LEN value along the way. Once all the data has been received, the bus controller will raise an interrupt indicating a packet command was completed, the slave address matched, a normal stop condition was seen, and the transfer was an RX operation. If the master sent a NACK instead of a normal stop condition, or the transfer timed out, then a slightly different set of interrupt status values would be set. Those conditions are not handled in this commit. The Zephyr firmware then collects data from the RX DMA buffer and clears the status register by writing the PKT_MODE_EN bit to the status register. In packet mode, clearing the packet mode interrupt enable bit also clears most of the other interrupt bits automatically (except for a few bits above it). Note: if the master transmit or receive functions were in use simultaneously with the slave mode receive functionality, then the master mode functions may have raised the interrupt line for the bus before the DMA slave transfer is complete. It's important to have the slave's interrupt status register clear throughout the receive operation, and if the slave attempts to raise the interrupt before the master interrupt status is cleared, then it needs to re-raise the interrupt once the master interrupt status is cleared. (And vice-versa). That's why in this commit, when the master interrupt status is cleared and the interrupt line is lowered, we call the slave interrupt _raise_ function, to see if the interrupt was pending. (And again, vice-versa). Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220630045133.32251-8-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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a8d48f59cd
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1c5d909f88
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@ -78,6 +78,18 @@ static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
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}
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}
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static inline void aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus *bus)
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{
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AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
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if (!bus->regs[R_I2CS_INTR_STS]) {
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return;
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}
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bus->controller->intr_status |= 1 << bus->id;
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qemu_irq_raise(aic->bus_get_irq(bus));
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}
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static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset,
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unsigned size)
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{
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@ -140,8 +152,17 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset,
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case A_I2CM_DMA_LEN_STS:
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case A_I2CC_DMA_ADDR:
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case A_I2CC_DMA_LEN:
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case A_I2CS_DEV_ADDR:
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case A_I2CS_DMA_RX_ADDR:
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case A_I2CS_DMA_LEN:
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case A_I2CS_CMD:
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case A_I2CS_INTR_CTRL:
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case A_I2CS_DMA_LEN_STS:
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/* Value is already set, don't do anything. */
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break;
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case A_I2CS_INTR_STS:
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break;
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case A_I2CM_CMD:
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value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus));
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break;
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@ -547,12 +568,7 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
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switch (offset) {
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case A_I2CC_FUN_CTRL:
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if (SHARED_FIELD_EX32(value, SLAVE_EN)) {
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qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
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__func__);
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break;
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}
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bus->regs[R_I2CC_FUN_CTRL] = value & 0x007dc3ff;
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bus->regs[R_I2CC_FUN_CTRL] = value;
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break;
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case A_I2CC_AC_TIMING:
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bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff;
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@ -580,6 +596,7 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
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bus->controller->intr_status &= ~(1 << bus->id);
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qemu_irq_lower(aic->bus_get_irq(bus));
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}
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aspeed_i2c_bus_raise_slave_interrupt(bus);
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break;
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}
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bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f);
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@ -668,15 +685,53 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
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case A_I2CC_DMA_LEN:
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/* RO */
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break;
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case A_I2CS_DMA_LEN_STS:
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case A_I2CS_DMA_TX_ADDR:
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case A_I2CS_DMA_RX_ADDR:
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case A_I2CS_DEV_ADDR:
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case A_I2CS_INTR_CTRL:
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case A_I2CS_INTR_STS:
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case A_I2CS_CMD:
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bus->regs[R_I2CS_DEV_ADDR] = value;
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break;
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case A_I2CS_DMA_RX_ADDR:
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bus->regs[R_I2CS_DMA_RX_ADDR] = value;
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break;
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case A_I2CS_DMA_LEN:
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qemu_log_mask(LOG_UNIMP, "%s: Slave mode is not implemented\n",
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assert(FIELD_EX32(value, I2CS_DMA_LEN, TX_BUF_LEN) == 0);
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if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) {
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ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN,
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FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN));
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} else {
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bus->regs[R_I2CS_DMA_LEN] = value;
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}
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break;
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case A_I2CS_CMD:
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if (FIELD_EX32(value, I2CS_CMD, W1_CTRL)) {
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bus->regs[R_I2CS_CMD] |= value;
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} else {
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bus->regs[R_I2CS_CMD] = value;
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}
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i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]);
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break;
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case A_I2CS_INTR_CTRL:
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bus->regs[R_I2CS_INTR_CTRL] = value;
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break;
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case A_I2CS_INTR_STS:
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if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) {
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if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) &&
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FIELD_EX32(value, I2CS_INTR_STS, PKT_CMD_DONE)) {
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bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000;
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}
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} else {
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bus->regs[R_I2CS_INTR_STS] &= ~value;
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}
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if (!bus->regs[R_I2CS_INTR_STS]) {
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bus->controller->intr_status &= ~(1 << bus->id);
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qemu_irq_lower(aic->bus_get_irq(bus));
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}
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aspeed_i2c_bus_raise_interrupt(bus);
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break;
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case A_I2CS_DMA_LEN_STS:
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bus->regs[R_I2CS_DMA_LEN_STS] = 0;
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break;
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case A_I2CS_DMA_TX_ADDR:
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qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n",
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__func__);
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break;
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default:
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@ -1037,6 +1092,39 @@ static const TypeInfo aspeed_i2c_info = {
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.abstract = true,
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};
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static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus,
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enum i2c_event event)
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{
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switch (event) {
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case I2C_START_SEND_ASYNC:
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if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Slave mode RX DMA is not enabled\n", __func__);
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return -1;
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}
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ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0);
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bus->regs[R_I2CC_DMA_ADDR] =
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ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR);
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bus->regs[R_I2CC_DMA_LEN] =
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ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1;
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i2c_ack(bus->bus);
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break;
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case I2C_FINISH:
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ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1);
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ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
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SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, NORMAL_STOP, 1);
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SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, RX_DONE, 1);
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aspeed_i2c_bus_raise_slave_interrupt(bus);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: i2c event %d unimplemented\n",
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__func__, event);
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return -1;
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}
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return 0;
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}
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static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
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{
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BusState *qbus = qdev_get_parent_bus(DEVICE(slave));
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@ -1045,6 +1133,10 @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
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uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
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uint32_t value;
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if (aspeed_i2c_is_new_mode(bus->controller)) {
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return aspeed_i2c_bus_new_slave_event(bus, event);
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}
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switch (event) {
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case I2C_START_SEND_ASYNC:
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value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
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@ -1073,6 +1165,19 @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
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return 0;
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}
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static void aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus *bus, uint8_t data)
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{
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assert(address_space_write(&bus->controller->dram_as,
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bus->regs[R_I2CC_DMA_ADDR],
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MEMTXATTRS_UNSPECIFIED, &data, 1) == MEMTX_OK);
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bus->regs[R_I2CC_DMA_ADDR]++;
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bus->regs[R_I2CC_DMA_LEN]--;
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ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN,
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ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN) + 1);
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i2c_ack(bus->bus);
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}
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static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data)
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{
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BusState *qbus = qdev_get_parent_bus(DEVICE(slave));
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uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
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uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
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if (aspeed_i2c_is_new_mode(bus->controller)) {
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return aspeed_i2c_bus_new_slave_send_async(bus, data);
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}
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SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data);
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SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
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@ -174,6 +174,8 @@ REG32(I2CM_DMA_LEN, 0x1c)
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FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
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FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11)
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REG32(I2CS_INTR_CTRL, 0x20)
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FIELD(I2CS_INTR_CTRL, PKT_CMD_FAIL, 17, 1)
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FIELD(I2CS_INTR_CTRL, PKT_CMD_DONE, 16, 1)
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REG32(I2CS_INTR_STS, 0x24)
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/* 31:29 shared with I2CD_INTR_STS[31:29] */
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FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2)
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@ -184,6 +186,7 @@ REG32(I2CS_INTR_STS, 0x24)
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FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1)
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FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1)
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/* 14:0 shared with I2CD_INTR_STS[14:0] */
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FIELD(I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1)
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REG32(I2CS_CMD, 0x28)
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FIELD(I2CS_CMD, W1_CTRL, 31, 1)
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FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2)
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