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target/tricore: Fix OPC2_32_RCRW_INSERT translation

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we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-02-02 13:04:25 +01:00
parent 76f7f54840
commit 1c6b2e4b79
1 changed files with 2 additions and 2 deletions
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target/tricore/translate.c
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@ -5805,8 +5805,8 @@ static void decode_rcrw_insert(DisasContext *ctx)
tcg_gen_movi_tl(temp, width);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_temp_free(temp3);
break;