target/openrisc: Increase the TLB size
The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- v2: - Change VMState version.
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@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s)
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
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UPR_PMP;
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UPR_PMP;
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
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| (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
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| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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cpu->env.picmr = 0x00000000;
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cpu->env.picmr = 0x00000000;
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@ -222,7 +222,7 @@ enum {
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/* TLB size */
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/* TLB size */
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enum {
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enum {
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TLB_SIZE = 64,
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TLB_SIZE = 128,
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TLB_MASK = TLB_SIZE - 1,
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TLB_MASK = TLB_SIZE - 1,
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};
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};
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@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = {
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static const VMStateDescription vmstate_cpu_tlb = {
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static const VMStateDescription vmstate_cpu_tlb = {
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.name = "cpu_tlb",
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.name = "cpu_tlb",
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id = 2,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
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VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
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vmstate_tlb_entry, OpenRISCTLBEntry),
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vmstate_tlb_entry, OpenRISCTLBEntry),
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