tcg/s390x: Support raising sigbus for user-only
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -29,6 +29,7 @@
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#error "unsupported code generation mode"
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#error "unsupported code generation mode"
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#endif
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#endif
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#include "../tcg-ldst.c.inc"
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#include "../tcg-pool.c.inc"
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#include "../tcg-pool.c.inc"
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#include "elf.h"
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#include "elf.h"
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@ -136,6 +137,7 @@ typedef enum S390Opcode {
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RI_OIHL = 0xa509,
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RI_OIHL = 0xa509,
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RI_OILH = 0xa50a,
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RI_OILH = 0xa50a,
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RI_OILL = 0xa50b,
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RI_OILL = 0xa50b,
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RI_TMLL = 0xa701,
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RIE_CGIJ = 0xec7c,
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RIE_CGIJ = 0xec7c,
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RIE_CGRJ = 0xec64,
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RIE_CGRJ = 0xec64,
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@ -1804,8 +1806,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
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}
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}
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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#include "../tcg-ldst.c.inc"
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/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
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/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
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@ -1942,6 +1942,53 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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return true;
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return true;
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}
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}
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#else
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld,
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TCGReg addrlo, unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *l = new_ldst_label(s);
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l->is_ld = is_ld;
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l->addrlo_reg = addrlo;
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/* We are expecting a_bits to max out at 7, much lower than TMLL. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_insn(s, RI, TMLL, addrlo, a_mask);
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tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
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l->label_ptr[0] = s->code_ptr;
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s->code_ptr += 1;
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l->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL,
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(intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
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return false;
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}
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tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg);
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
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/* "Tail call" to the helper, with the return address back inline. */
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr);
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tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unaligned_ld
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: helper_unaligned_st));
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return true;
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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return tcg_out_fail_alignment(s, l);
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}
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static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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return tcg_out_fail_alignment(s, l);
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}
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static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
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static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
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TCGReg *index_reg, tcg_target_long *disp)
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TCGReg *index_reg, tcg_target_long *disp)
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{
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{
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@ -1980,7 +2027,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
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#else
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#else
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TCGReg index_reg;
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TCGReg index_reg;
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tcg_target_long disp;
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tcg_target_long disp;
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addr_reg, a_bits);
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}
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tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
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tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
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tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
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tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
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#endif
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#endif
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@ -2007,7 +2058,11 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
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#else
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#else
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TCGReg index_reg;
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TCGReg index_reg;
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tcg_target_long disp;
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tcg_target_long disp;
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, false, addr_reg, a_bits);
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}
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tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
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tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
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tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
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tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
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#endif
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#endif
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@ -178,9 +178,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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/* no need to flush icache explicitly */
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/* no need to flush icache explicitly */
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}
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}
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#define TCG_TARGET_NEED_POOL_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif
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#endif
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