tcg/aarch64: Detect have_lse, have_lse2 for darwin
These features are present for Apple M1. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -16,6 +16,9 @@
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#ifdef __linux__
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#ifdef __linux__
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#include <asm/hwcap.h>
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#include <asm/hwcap.h>
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#endif
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#endif
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#ifdef CONFIG_DARWIN
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#include <sys/sysctl.h>
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#endif
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/* We're going to re-use TCGType in setting of the SF bit, which controls
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/* We're going to re-use TCGType in setting of the SF bit, which controls
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the size of the operation performed. If we know the values match, it
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the size of the operation performed. If we know the values match, it
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@ -2903,6 +2906,27 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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}
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}
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}
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}
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#ifdef CONFIG_DARWIN
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static bool sysctl_for_bool(const char *name)
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{
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int val = 0;
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size_t len = sizeof(val);
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if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
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return val != 0;
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}
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/*
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* We might in the future ask for properties not present in older kernels,
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* but we're only asking about static properties, all of which should be
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* 'int'. So we shouln't see ENOMEM (val too small), or any of the other
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* more exotic errors.
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*/
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assert(errno == ENOENT);
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return false;
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}
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#endif
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static void tcg_target_init(TCGContext *s)
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static void tcg_target_init(TCGContext *s)
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{
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{
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#ifdef __linux__
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#ifdef __linux__
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@ -2910,6 +2934,10 @@ static void tcg_target_init(TCGContext *s)
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have_lse = hwcap & HWCAP_ATOMICS;
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have_lse = hwcap & HWCAP_ATOMICS;
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have_lse2 = hwcap & HWCAP_USCAT;
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have_lse2 = hwcap & HWCAP_USCAT;
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#endif
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#endif
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#ifdef CONFIG_DARWIN
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have_lse = sysctl_for_bool("hw.optional.arm.FEAT_LSE");
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have_lse2 = sysctl_for_bool("hw.optional.arm.FEAT_LSE2");
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#endif
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
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