xhci: create a memory region for each port
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann
parent
ccaf87a085
commit
1d8a4e69ee
@ -285,6 +285,8 @@ typedef enum TRBCCode {
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#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
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#define SLOT_CONTEXT_ENTRIES_SHIFT 27
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typedef struct XHCIState XHCIState;
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typedef enum EPType {
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ET_INVALID = 0,
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ET_ISO_OUT,
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@ -303,15 +305,15 @@ typedef struct XHCIRing {
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} XHCIRing;
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typedef struct XHCIPort {
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XHCIState *xhci;
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uint32_t portsc;
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uint32_t portnr;
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USBPort *uport;
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uint32_t speedmask;
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char name[16];
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MemoryRegion mem;
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} XHCIPort;
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struct XHCIState;
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typedef struct XHCIState XHCIState;
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typedef struct XHCITransfer {
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XHCIState *xhci;
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USBPacket packet;
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@ -2430,20 +2432,14 @@ static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
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return ret;
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}
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static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
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static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
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{
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uint32_t port = reg >> 4;
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XHCIPort *port = ptr;
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uint32_t ret;
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if (port >= xhci->numports) {
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fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
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ret = 0;
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goto out;
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}
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switch (reg & 0xf) {
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switch (reg) {
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case 0x00: /* PORTSC */
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ret = xhci->ports[port].portsc;
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ret = port->portsc;
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break;
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case 0x04: /* PORTPMSC */
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case 0x08: /* PORTLI */
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@ -2452,30 +2448,25 @@ static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
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case 0x0c: /* reserved */
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default:
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fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
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port, reg);
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port->portnr, (uint32_t)reg);
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ret = 0;
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}
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out:
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trace_usb_xhci_port_read(port, reg & 0x0f, ret);
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trace_usb_xhci_port_read(port->portnr, reg, ret);
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return ret;
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}
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static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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static void xhci_port_write(void *ptr, target_phys_addr_t reg,
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uint64_t val, unsigned size)
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{
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uint32_t port = reg >> 4;
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XHCIPort *port = ptr;
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uint32_t portsc;
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trace_usb_xhci_port_write(port, reg & 0x0f, val);
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trace_usb_xhci_port_write(port->portnr, reg, val);
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if (port >= xhci->numports) {
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fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
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return;
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}
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switch (reg & 0xf) {
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switch (reg) {
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case 0x00: /* PORTSC */
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portsc = xhci->ports[port].portsc;
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portsc = port->portsc;
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/* write-1-to-clear bits*/
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portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
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PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
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@ -2490,16 +2481,16 @@ static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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/* write-1-to-start bits */
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if (val & PORTSC_PR) {
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DPRINTF("xhci: port %d reset\n", port);
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usb_device_reset(xhci->ports[port].uport->dev);
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usb_device_reset(port->uport->dev);
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portsc |= PORTSC_PRC | PORTSC_PED;
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}
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xhci->ports[port].portsc = portsc;
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port->portsc = portsc;
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break;
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case 0x04: /* PORTPMSC */
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case 0x08: /* PORTLI */
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default:
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fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
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port, reg);
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port->portnr, (uint32_t)reg);
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}
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}
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@ -2508,10 +2499,6 @@ static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
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XHCIState *xhci = ptr;
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uint32_t ret;
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if (reg >= 0x400) {
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return xhci_port_read(xhci, reg - 0x400);
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}
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switch (reg) {
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case 0x00: /* USBCMD */
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ret = xhci->usbcmd;
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@ -2554,11 +2541,6 @@ static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
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{
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XHCIState *xhci = ptr;
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if (reg >= 0x400) {
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xhci_port_write(xhci, reg - 0x400, val);
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return;
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}
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trace_usb_xhci_oper_write(reg, val);
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switch (reg) {
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@ -2777,6 +2759,14 @@ static const MemoryRegionOps xhci_oper_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps xhci_port_ops = {
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.read = xhci_port_read,
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.write = xhci_port_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps xhci_runtime_ops = {
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.read = xhci_runtime_read,
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.write = xhci_runtime_write,
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@ -2850,7 +2840,7 @@ static void xhci_child_detach(USBPort *uport, USBDevice *child)
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}
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}
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static USBPortOps xhci_port_ops = {
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static USBPortOps xhci_uport_ops = {
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.attach = xhci_attach,
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.detach = xhci_detach,
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.wakeup = xhci_wakeup,
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@ -2930,6 +2920,7 @@ static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
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USB_SPEED_MASK_LOW |
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USB_SPEED_MASK_FULL |
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USB_SPEED_MASK_HIGH;
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snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
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speedmask |= port->speedmask;
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}
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if (i < xhci->numports_3) {
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@ -2937,16 +2928,17 @@ static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
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port->portnr = i + 1 + xhci->numports_2;
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port->uport = &xhci->uports[i];
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port->speedmask = USB_SPEED_MASK_SUPER;
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snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
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speedmask |= port->speedmask;
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}
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usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
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&xhci_port_ops, speedmask);
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&xhci_uport_ops, speedmask);
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}
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}
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static int usb_xhci_initfn(struct PCIDevice *dev)
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{
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int ret;
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int i, ret;
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XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
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@ -2965,7 +2957,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
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"capabilities", LEN_CAP);
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memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci,
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"operational", 0x400 + 0x10 * xhci->numports);
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"operational", 0x400);
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memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci,
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"runtime", LEN_RUNTIME);
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memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci,
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@ -2976,6 +2968,15 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
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memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
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for (i = 0; i < xhci->numports; i++) {
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XHCIPort *port = &xhci->ports[i];
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uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
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port->xhci = xhci;
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memory_region_init_io(&port->mem, &xhci_port_ops, port,
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port->name, 0x10);
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memory_region_add_subregion(&xhci->mem, offset, &port->mem);
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}
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pci_register_bar(&xhci->pci_dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
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&xhci->mem);
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