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target/riscv: Fix implementation of HLVX.WU instruction 

The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.

Fixes: 8c5362acb5 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Georg Kotheimer 2020-10-13 19:22:23 +02:00 committed by Alistair Francis
parent 4aeb9e26c2
commit 1da46012ea
1 changed files with 3 additions and 3 deletions
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6
target/riscv/op_helper.c
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@ -333,12 +333,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) {
case MO_TEUL:
pte = cpu_ldub_data_ra(env, address, GETPC());
break;
case MO_TEUW:
pte = cpu_lduw_data_ra(env, address, GETPC());
break;
case MO_TEUL:
pte = cpu_ldl_data_ra(env, address, GETPC());
break;
default:
g_assert_not_reached();
}