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Hexagon (target/hexagon) Add pkt and insn to DisasContext 

This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments

Not only does this simplify the code, it improves the translation time

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221108162906.3166-2-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2022-11-08 08:28:56 -08:00
parent 4208e6ae11
commit 1e536334cc
8 changed files with 89 additions and 88 deletions
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15
target/hexagon/gen_tcg_funcs.py
View File

@ -561,11 +561,7 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## Generate the TCG code to call the helper
## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
## We produce:
## static void generate_A2_add()
## CPUHexagonState *env
## DisasContext *ctx,
## Insn *insn,
## Packet *pkt)
## static void generate_A2_add(DisasContext *ctx)
## {
## TCGv RdV = tcg_temp_local_new();
## const int RdN = insn->regno[0];
@ -584,12 +580,11 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## <GEN> is gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
##
def gen_tcg_func(f, tag, regs, imms):
f.write("static void generate_%s(\n" %tag)
f.write(" CPUHexagonState *env,\n")
f.write(" DisasContext *ctx,\n")
f.write(" Insn *insn,\n")
f.write(" Packet *pkt)\n")
f.write("static void generate_%s(DisasContext *ctx)\n" %tag)
f.write('{\n')
f.write(" Insn *insn __attribute__((unused)) = ctx->insn;\n")
if hex_common.need_ea(tag): gen_decl_ea_tcg(f, tag)
i=0
## Declare all the operands (regs and immediates)

6
target/hexagon/gen_tcg_hvx.h
View File

@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -697,7 +697,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
#define fGEN_TCG_NEWVAL_VEC_STORE(GET_EA, INC) \
do { \
GET_EA; \
gen_vreg_store(ctx, insn, pkt, EA, OsN_off, insn->slot, true); \
gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \
INC; \
} while (0)
@ -736,7 +736,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
PRED; \
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
tcg_temp_free(LSB); \
gen_vreg_store(ctx, insn, pkt, EA, SRCOFF, insn->slot, ALIGN); \
gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \
INC; \
tcg_gen_br(end_label); \
gen_set_label(false_label); \

6
target/hexagon/genptr.c
View File

@ -551,13 +551,13 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
tcg_temp_free_i64(tmp);
}
static void gen_vreg_store(DisasContext *ctx, Insn *insn, Packet *pkt,
TCGv EA, intptr_t srcoff, int slot, bool aligned)
static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff,
int slot, bool aligned)
{
intptr_t dstoff = offsetof(CPUHexagonState, vstore[slot].data);
intptr_t maskoff = offsetof(CPUHexagonState, vstore[slot].mask);
if (is_gather_store_insn(insn, pkt)) {
if (is_gather_store_insn(ctx)) {
TCGv sl = tcg_constant_tl(slot);
gen_helper_gather_store(cpu_env, EA, sl);
return;

7
target/hexagon/insn.h
View File

@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -28,10 +28,7 @@ struct Instruction;
struct Packet;
struct DisasContext;
typedef void (*SemanticInsn)(CPUHexagonState *env,
struct DisasContext *ctx,
struct Instruction *insn,
struct Packet *pkt);
typedef void (*SemanticInsn)(struct DisasContext *ctx);
struct Instruction {
SemanticInsn generate; /* pointer to genptr routine */

10
target/hexagon/macros.h
View File

@ -94,9 +94,9 @@
*/
#define CHECK_NOSHUF(VA, SIZE) \
do { \
if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
process_store(ctx, pkt, 1); \
process_store(ctx, 1); \
} \
} while (0)
@ -105,12 +105,12 @@
TCGLabel *label = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
GET_EA; \
if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
} \
gen_set_label(label); \
if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
process_store(ctx, pkt, 1); \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
process_store(ctx, 1); \
} \
} while (0)

4
target/hexagon/mmvec/macros.h
View File

@ -288,7 +288,7 @@
#endif
#ifdef QEMU_GENERATE
#define fSTOREMMV(EA, SRC) \
gen_vreg_store(ctx, insn, pkt, EA, SRC##_off, insn->slot, true)
gen_vreg_store(ctx, EA, SRC##_off, insn->slot, true)
#endif
#ifdef QEMU_GENERATE
#define fSTOREMMVQ(EA, SRC, MASK) \
@ -300,7 +300,7 @@
#endif
#ifdef QEMU_GENERATE
#define fSTOREMMVU(EA, SRC) \
gen_vreg_store(ctx, insn, pkt, EA, SRC##_off, insn->slot, false)
gen_vreg_store(ctx, EA, SRC##_off, insn->slot, false)
#endif
#define fVFOREACH(WIDTH, VAR) for (VAR = 0; VAR < fVELEM(WIDTH); VAR++)
#define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \

120
target/hexagon/translate.c
View File

@ -209,8 +209,9 @@ static bool need_pred_written(Packet *pkt)
return check_for_attrib(pkt, A_WRITES_PRED_REG);
}
static void gen_start_packet(DisasContext *ctx, Packet *pkt)
static void gen_start_packet(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
int i;
@ -260,8 +261,10 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
}
}
bool is_gather_store_insn(Insn *insn, Packet *pkt)
bool is_gather_store_insn(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
Insn *insn = ctx->insn;
if (GET_ATTRIB(insn->opcode, A_CVI_NEW) &&
insn->new_value_producer_slot == 1) {
/* Look for gather instruction */
@ -280,15 +283,15 @@ bool is_gather_store_insn(Insn *insn, Packet *pkt)
* However, there are some implicit writes marked as attributes
* of the applicable instructions.
*/
static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
int attrib, int rnum)
static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum)
{
if (GET_ATTRIB(insn->opcode, attrib)) {
uint16_t opcode = ctx->insn->opcode;
if (GET_ATTRIB(opcode, attrib)) {
/*
* USR is used to set overflow and FP exceptions,
* so treat it as conditional
*/
bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) ||
bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) ||
rnum == HEX_REG_USR;
if (is_predicated && !is_preloaded(ctx, rnum)) {
tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
@ -298,39 +301,38 @@ static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
}
}
static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn,
int attrib, int pnum)
static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum)
{
if (GET_ATTRIB(insn->opcode, attrib)) {
if (GET_ATTRIB(ctx->insn->opcode, attrib)) {
ctx_log_pred_write(ctx, pnum);
}
}
static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
static void mark_implicit_reg_writes(DisasContext *ctx)
{
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR);
}
static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
static void mark_implicit_pred_writes(DisasContext *ctx)
{
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3);
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0);
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1);
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2);
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3);
}
static void mark_store_width(DisasContext *ctx, Insn *insn)
static void mark_store_width(DisasContext *ctx)
{
uint16_t opcode = insn->opcode;
uint32_t slot = insn->slot;
uint16_t opcode = ctx->insn->opcode;
uint32_t slot = ctx->insn->slot;
uint8_t width = 0;
if (GET_ATTRIB(opcode, A_SCALAR_STORE)) {
@ -351,14 +353,13 @@ static void mark_store_width(DisasContext *ctx, Insn *insn)
}
}
static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
Insn *insn, Packet *pkt)
static void gen_insn(DisasContext *ctx)
{
if (insn->generate) {
mark_implicit_reg_writes(ctx, insn);
insn->generate(env, ctx, insn, pkt);
mark_implicit_pred_writes(ctx, insn);
mark_store_width(ctx, insn);
if (ctx->insn->generate) {
mark_implicit_reg_writes(ctx);
ctx->insn->generate(ctx);
mark_implicit_pred_writes(ctx);
mark_store_width(ctx);
} else {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
}
@ -378,7 +379,7 @@ static void gen_reg_writes(DisasContext *ctx)
}
}
static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
static void gen_pred_writes(DisasContext *ctx)
{
int i;
@ -393,7 +394,7 @@ static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
* instructions, we can use the non-conditional
* write of the predicates.
*/
if (pkt->pkt_has_endloop) {
if (ctx->pkt->pkt_has_endloop) {
TCGv zero = tcg_constant_tl(0);
TCGv pred_written = tcg_temp_new();
for (i = 0; i < ctx->preg_log_idx; i++) {
@ -439,9 +440,9 @@ static bool slot_is_predicated(Packet *pkt, int slot_num)
g_assert_not_reached();
}
void process_store(DisasContext *ctx, Packet *pkt, int slot_num)
void process_store(DisasContext *ctx, int slot_num)
{
bool is_predicated = slot_is_predicated(pkt, slot_num);
bool is_predicated = slot_is_predicated(ctx->pkt, slot_num);
TCGLabel *label_end = NULL;
/*
@ -517,27 +518,28 @@ void process_store(DisasContext *ctx, Packet *pkt, int slot_num)
}
}
static void process_store_log(DisasContext *ctx, Packet *pkt)
static void process_store_log(DisasContext *ctx)
{
/*
* When a packet has two stores, the hardware processes
* slot 1 and then slot 0. This will be important when
* the memory accesses overlap.
*/
Packet *pkt = ctx->pkt;
if (pkt->pkt_has_store_s1) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, pkt, 1);
process_store(ctx, 1);
}
if (pkt->pkt_has_store_s0) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, pkt, 0);
process_store(ctx, 0);
}
}
/* Zero out a 32-bit cache line */
static void process_dczeroa(DisasContext *ctx, Packet *pkt)
static void process_dczeroa(DisasContext *ctx)
{
if (pkt->pkt_has_dczeroa) {
if (ctx->pkt->pkt_has_dczeroa) {
/* Store 32 bytes of zero starting at (addr & ~0x1f) */
TCGv addr = tcg_temp_new();
TCGv_i64 zero = tcg_constant_i64(0);
@ -567,7 +569,7 @@ static bool pkt_has_hvx_store(Packet *pkt)
return false;
}
static void gen_commit_hvx(DisasContext *ctx, Packet *pkt)
static void gen_commit_hvx(DisasContext *ctx)
{
int i;
@ -637,13 +639,14 @@ static void gen_commit_hvx(DisasContext *ctx, Packet *pkt)
}
}
if (pkt_has_hvx_store(pkt)) {
if (pkt_has_hvx_store(ctx->pkt)) {
gen_helper_commit_hvx_stores(cpu_env);
}
}
static void update_exec_counters(DisasContext *ctx, Packet *pkt)
static void update_exec_counters(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
int num_insns = pkt->num_insns;
int num_real_insns = 0;
int num_hvx_insns = 0;
@ -664,8 +667,7 @@ static void update_exec_counters(DisasContext *ctx, Packet *pkt)
ctx->num_hvx_insns += num_hvx_insns;
}
static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
Packet *pkt)
static void gen_commit_packet(DisasContext *ctx)
{
/*
* If there is more than one store in a packet, make sure they are all OK
@ -684,6 +686,7 @@ static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
* store. Therefore, we call process_store_log before anything else
* involved in committing the packet.
*/
Packet *pkt = ctx->pkt;
bool has_store_s0 = pkt->pkt_has_store_s0;
bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
bool has_hvx_store = pkt_has_hvx_store(pkt);
@ -693,7 +696,7 @@ static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
* a store in slot 1 or an HVX store.
*/
g_assert(!has_store_s1 && !has_hvx_store);
process_dczeroa(ctx, pkt);
process_dczeroa(ctx);
} else if (has_hvx_store) {
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
@ -724,14 +727,14 @@ static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
}
process_store_log(ctx, pkt);
process_store_log(ctx);
gen_reg_writes(ctx);
gen_pred_writes(ctx, pkt);
gen_pred_writes(ctx);
if (pkt->pkt_has_hvx) {
gen_commit_hvx(ctx, pkt);
gen_commit_hvx(ctx);
}
update_exec_counters(ctx, pkt);
update_exec_counters(ctx);
if (HEX_DEBUG) {
TCGv has_st0 =
tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
@ -744,7 +747,8 @@ static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
if (pkt->vhist_insn != NULL) {
ctx->pre_commit = false;
pkt->vhist_insn->generate(env, ctx, pkt->vhist_insn, pkt);
ctx->insn = pkt->vhist_insn;
pkt->vhist_insn->generate(ctx);
}
if (pkt->pkt_has_cof) {
@ -767,11 +771,13 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
if (decode_packet(nwords, words, &pkt, false) > 0) {
HEX_DEBUG_PRINT_PKT(&pkt);
gen_start_packet(ctx, &pkt);
ctx->pkt = &pkt;
gen_start_packet(ctx);
for (i = 0; i < pkt.num_insns; i++) {
gen_insn(env, ctx, &pkt.insn[i], &pkt);
ctx->insn = &pkt.insn[i];
gen_insn(ctx);
}
gen_commit_packet(env, ctx, &pkt);
gen_commit_packet(ctx);
ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
} else {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);

9
target/hexagon/translate.h
View File

@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -23,10 +23,13 @@
#include "cpu.h"
#include "exec/translator.h"
#include "tcg/tcg-op.h"
#include "insn.h"
#include "internal.h"
typedef struct DisasContext {
DisasContextBase base;
Packet *pkt;
Insn *insn;
uint32_t mem_idx;
uint32_t num_packets;
uint32_t num_insns;
@ -147,6 +150,6 @@ extern TCGv hex_vstore_addr[VSTORES_MAX];
extern TCGv hex_vstore_size[VSTORES_MAX];
extern TCGv hex_vstore_pending[VSTORES_MAX];
bool is_gather_store_insn(Insn *insn, Packet *pkt);
void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
bool is_gather_store_insn(DisasContext *ctx);
void process_store(DisasContext *ctx, int slot_num);
#endif