SH: On-chip PCI controller support (Takashi YOSHII).
This patch adds SuperH on-chip PCI controller(PCIC) support. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
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balrog
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@ -710,7 +710,7 @@ CPPFLAGS += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_BASE_ARCH), sh4)
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OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
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OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
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OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
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OBJS+= ide.o
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endif
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ifeq ($(TARGET_BASE_ARCH), m68k)
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207
hw/sh_pci.c
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207
hw/sh_pci.c
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@ -0,0 +1,207 @@
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/*
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* SuperH on-chip PCIC emulation.
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*
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* Copyright (c) 2008 Takashi YOSHII
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sh.h"
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#include "pci.h"
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#include "bswap.h"
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typedef struct {
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PCIBus *bus;
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PCIDevice *dev;
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uint32_t regbase;
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uint32_t iopbase;
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uint32_t membase;
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uint32_t par;
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uint32_t mbr;
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uint32_t iobr;
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} SHPCIC;
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static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
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{
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SHPCIC *pcic = p;
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addr -= pcic->regbase;
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switch(addr) {
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case 0 ... 0xfc:
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cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
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break;
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case 0x1c0:
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pcic->par = val;
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break;
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case 0x1c4:
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pcic->mbr = val;
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break;
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case 0x1c8:
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pcic->iobr = val;
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break;
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case 0x220:
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pci_data_write(pcic->bus, pcic->par, val, 4);
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break;
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}
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}
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static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
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{
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SHPCIC *pcic = p;
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addr -= pcic->regbase;
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switch(addr) {
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case 0 ... 0xfc:
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return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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case 0x1c0:
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return pcic->par;
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case 0x220:
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return pci_data_read(pcic->bus, pcic->par, 4);
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}
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return 0;
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}
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static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
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uint32_t val, int size)
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{
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pci_data_write(pcic->bus, addr - pcic->membase + pcic->mbr, val, size);
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}
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static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
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int size)
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{
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return pci_data_read(pcic->bus, addr - pcic->membase + pcic->mbr, size);
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}
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static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
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{
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sh_pci_data_write(p, addr, val, 1);
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}
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static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)
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{
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sh_pci_data_write(p, addr, val, 2);
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}
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static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)
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{
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sh_pci_data_write(p, addr, val, 4);
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}
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static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)
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{
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return sh_pci_mem_read(p, addr, 1);
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}
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static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)
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{
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return sh_pci_mem_read(p, addr, 2);
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}
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static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
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{
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return sh_pci_mem_read(p, addr, 4);
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}
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static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
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{
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return addr - pcic->iopbase + pcic->iobr;
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}
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static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
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{
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cpu_outb(NULL, sh_pci_addr2port(p, addr), val);
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}
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static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)
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{
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cpu_outw(NULL, sh_pci_addr2port(p, addr), val);
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}
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static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)
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{
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cpu_outl(NULL, sh_pci_addr2port(p, addr), val);
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}
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static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)
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{
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return cpu_inb(NULL, sh_pci_addr2port(p, addr));
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}
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static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)
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{
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return cpu_inw(NULL, sh_pci_addr2port(p, addr));
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}
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static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
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{
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return cpu_inl(NULL, sh_pci_addr2port(p, addr));
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}
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typedef struct {
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CPUReadMemoryFunc *r[3];
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CPUWriteMemoryFunc *w[3];
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} MemOp;
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static MemOp sh_pci_reg = {
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{ NULL, NULL, sh_pci_reg_read },
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{ NULL, NULL, sh_pci_reg_write },
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};
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static MemOp sh_pci_mem = {
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{ sh_pci_readb, sh_pci_readw, sh_pci_readl },
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{ sh_pci_writeb, sh_pci_writew, sh_pci_writel },
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};
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static MemOp sh_pci_iop = {
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{ sh_pci_inb, sh_pci_inw, sh_pci_inl },
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{ sh_pci_outb, sh_pci_outw, sh_pci_outl },
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};
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PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq)
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{
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SHPCIC *p;
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int mem, reg, iop;
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p = qemu_mallocz(sizeof(SHPCIC));
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p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);
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p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
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-1, NULL, NULL);
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p->regbase = 0x1e200000;
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p->iopbase = 0x1e240000;
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p->membase = 0xfd000000;
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reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
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mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
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iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
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cpu_register_physical_memory(p->regbase, 0x224, reg);
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cpu_register_physical_memory(p->iopbase, 0x40000, iop);
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cpu_register_physical_memory(p->membase, 0x1000000, mem);
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p->dev->config[0x00] = 0x54; // HITACHI
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p->dev->config[0x01] = 0x10; //
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p->dev->config[0x02] = 0x0e; // SH7751R
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p->dev->config[0x03] = 0x35; //
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p->dev->config[0x04] = 0x80;
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p->dev->config[0x05] = 0x00;
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p->dev->config[0x06] = 0x90;
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p->dev->config[0x07] = 0x02;
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return p->bus;
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}
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@ -439,6 +439,9 @@ int get_physical_address(CPUState * env, target_ulong * physical,
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if (address >= 0x80000000 && address < 0xc0000000) {
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/* Mask upper 3 bits for P1 and P2 areas */
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*physical = address & 0x1fffffff;
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} else if (address >= 0xfd000000 && address < 0xfe000000) {
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/* PCI memory space */
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*physical = address;
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} else if (address >= 0xfc000000) {
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/*
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* Mask upper 3 bits for control registers in P4 area,
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