ppc patch queue 20200720

Here are some assorted fixes for qemu-5.1: * SLOF update with improved TPM handling, and fix for possible stack overflows on many-vcpu machines * Fix for NUMA distances on NVLink2 attached GPU memory nodes * Fixes to fail more gracefully on attempting to plug unsupported PCI bridge types * Don't allow pnv-psi device to be user created -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl8VK7EACgkQbDjKyiDZ s5K7HxAAjFAzlKD7AiF7u0TbuvBFx3J3zxIcCnd3W0ViBiZ4FOybjf7/q8R8Wu94 MrNv/15fZLbS6rcUCERFnEr+TpFgZ/mUn0JuoJWI0AUrI+FtUaCj9kznjwfzU0jN gU75F6R5q1GzS8ENHZWm1xWHVTk3OBj1eWQu8ialx9Kx4TMc9hTdgIYhQoB6+WD3 nyIR6FUlMutYvPcODJS/HHLLT9Nc3w0zQAOYz7B+OgBKWkM61H3L17ITg9eo9YDz /xPz+41DqYC1FsTcTB91572lbePCURScJc2xE8GvuGMwNmdDoTMq+EALCLlTawIJ 68w6e+y4uymnDwSGRn0j3Wopc6iggEbeIukgO1GZLUwyACOLWXtwGh3SOxEcmsYH CiUgBkZ0k07lyXAlMmpIwrc90qPXh7Ox4m24DsH+A0eSNPUtuWOht4dLrHbuAkkf 5KMhTBWMOnLxUilrp+U3Xsuo5BUQVAy6eBI1sCYaLHTJIFoBg0G0g7xg7q/23nnc DX0RtZgjJdlFjfbzFzetSJYzd8Xf5P9Giqx0XZ+w6vpPTXBsDA57MqpICXiEQGSk OeVp51dWrWL1FIRoEL1O7YZBu57Oi1hpl1JVG3bxCKa+lxiVw6ZLXGL9m8otOc1/ iSr3WpTI9wOo5Ele3lkl0NQjNeGnJ401UpmGCkEclp2zmMdCGrU= =CYAQ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200720' into staging ppc patch queue 20200720 Here are some assorted fixes for qemu-5.1: * SLOF update with improved TPM handling, and fix for possible stack overflows on many-vcpu machines * Fix for NUMA distances on NVLink2 attached GPU memory nodes * Fixes to fail more gracefully on attempting to plug unsupported PCI bridge types * Don't allow pnv-psi device to be user created # gpg: Signature made Mon 20 Jul 2020 06:29:21 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.1-20200720: pseries: Update SLOF firmware image spapr: Add a new level of NUMA for GPUs spapr_pci: Robustify support of PCI bridges ppc/pnv: Make PSI device types not user creatable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-20 11:34:10 +01:00 · 2020-07-20 11:34:10 +01:00 · 1e6c50ad85
parent 873ec69aeb b25fbd6a13
commit 1e6c50ad85
9 changed files with 90 additions and 7 deletions
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@ -929,6 +929,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data)
    dc->desc = "PowerNV PSI Controller";
    device_class_set_props(dc, pnv_psi_properties);
    dc->reset = pnv_psi_reset;
+    dc->user_creatable = false;
 }

 static const TypeInfo pnv_psi_info = {
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@ -890,10 +890,16 @@ static int spapr_dt_rng(void *fdt)
 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
 {
    MachineState *ms = MACHINE(spapr);
+    SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
    int rtas;
    GString *hypertas = g_string_sized_new(256);
    GString *qemu_hypertas = g_string_sized_new(256);
-    uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
+    uint32_t refpoints[] = {
+        cpu_to_be32(0x4),
+        cpu_to_be32(0x4),
+        cpu_to_be32(0x2),
+    };
+    uint32_t nr_refpoints = ARRAY_SIZE(refpoints);
    uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
        memory_region_size(&MACHINE(spapr)->device_memory->mr);
    uint32_t lrdr_capacity[] = {
@ -945,8 +951,12 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
                     qemu_hypertas->str, qemu_hypertas->len));
    g_string_free(qemu_hypertas, TRUE);

+    if (smc->pre_5_1_assoc_refpoints) {
+        nr_refpoints = 2;
+    }
+
    _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
-                     refpoints, sizeof(refpoints)));
+                     refpoints, nr_refpoints * sizeof(refpoints[0])));

    _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
                     maxdomains, sizeof(maxdomains)));
@ -4584,9 +4594,16 @@ DEFINE_SPAPR_MACHINE(5_1, "5.1", true);
 */
 static void spapr_machine_5_0_class_options(MachineClass *mc)
 {
+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
+    static GlobalProperty compat[] = {
+        { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" },
+    };
+
    spapr_machine_5_1_class_options(mc);
    compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
+    compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
    mc->numa_mem_supported = true;
+    smc->pre_5_1_assoc_refpoints = true;
 }

 DEFINE_SPAPR_MACHINE(5_0, "5.0", false);
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@ -1480,6 +1480,57 @@ static void spapr_pci_bridge_plug(SpaprPhbState *phb,
    add_drcs(phb, bus);
 }

+/* Returns non-zero if the value of "chassis_nr" is already in use */
+static int check_chassis_nr(Object *obj, void *opaque)
+{
+    int new_chassis_nr =
+        object_property_get_uint(opaque, "chassis_nr", &error_abort);
+    int chassis_nr =
+        object_property_get_uint(obj, "chassis_nr", NULL);
+
+    if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {
+        return 0;
+    }
+
+    /* Skip unsupported bridge types */
+    if (!chassis_nr) {
+        return 0;
+    }
+
+    /* Skip self */
+    if (obj == opaque) {
+        return 0;
+    }
+
+    return chassis_nr == new_chassis_nr;
+}
+
+static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)
+{
+    int chassis_nr =
+        object_property_get_uint(bridge, "chassis_nr", NULL);
+
+    /*
+     * slotid_cap_init() already ensures that "chassis_nr" isn't null for
+     * standard PCI bridges, so this really tells if "chassis_nr" is present
+     * or not.
+     */
+    if (!chassis_nr) {
+        error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");
+        error_append_hint(errp, "Try -device pci-bridge instead.\n");
+        return false;
+    }
+
+    /* We want unique values for "chassis_nr" */
+    if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,
+                                       bridge)) {
+        error_setg(errp, "Bridge chassis %d already in use", chassis_nr);
+        return false;
+    }
+
+    return true;
+}
+
 static void spapr_pci_plug(HotplugHandler *plug_handler,
                           DeviceState *plugged_dev, Error **errp)
 {
@ -1508,6 +1559,9 @@ static void spapr_pci_plug(HotplugHandler *plug_handler,
    g_assert(drc);

    if (pc->is_bridge) {
+        if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {
+            return;
+        }
        spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));
    }

@ -2035,6 +2089,8 @@ static Property spapr_phb_properties[] = {
                     pcie_ecs, true),
    DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),
    DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),
+    DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
+                     pre_5_1_assoc, false),
    DEFINE_PROP_END_OF_LIST(),
 };

--- a/hw/ppc/spapr_pci_nvlink2.c
+++ b/hw/ppc/spapr_pci_nvlink2.c
@ -362,9 +362,9 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
                                                    &error_abort);
        uint32_t associativity[] = {
            cpu_to_be32(0x4),
-            SPAPR_GPU_NUMA_ID,
-            SPAPR_GPU_NUMA_ID,
-            SPAPR_GPU_NUMA_ID,
+            cpu_to_be32(nvslot->numa_id),
+            cpu_to_be32(nvslot->numa_id),
+            cpu_to_be32(nvslot->numa_id),
            cpu_to_be32(nvslot->numa_id)
        };
        uint64_t size = object_property_get_uint(nv_mrobj, "size", NULL);
@ -375,6 +375,13 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
        _FDT(off);
        _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
        _FDT((fdt_setprop(fdt, off, "reg", mem_reg, sizeof(mem_reg))));
+
+        if (sphb->pre_5_1_assoc) {
+            associativity[1] = SPAPR_GPU_NUMA_ID;
+            associativity[2] = SPAPR_GPU_NUMA_ID;
+            associativity[3] = SPAPR_GPU_NUMA_ID;
+        }
+
        _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
                          sizeof(associativity))));

--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@ -94,6 +94,7 @@ struct SpaprPhbState {
    hwaddr nv2_gpa_win_addr;
    hwaddr nv2_atsd_win_addr;
    SpaprPhbPciNvGpuConfig *nvgpus;
+    bool pre_5_1_assoc;
 };

 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@ -129,6 +129,7 @@ struct SpaprMachineClass {
    bool linux_pci_probe;
    bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
    hwaddr rma_limit;          /* clamp the RMA to this size */
+    bool pre_5_1_assoc_refpoints;

    void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
                          uint64_t *buid, hwaddr *pio, 
--- a/pc-bios/README
+++ b/pc-bios/README
@ -14,7 +14,7 @@
 - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
  implementation for certain IBM POWER hardware.  The sources are at
  https://github.com/aik/SLOF, and the image currently in qemu is
-  built from git tag qemu-slof-20200327.
+  built from git tag qemu-slof-20200717.

 - sgabios (the Serial Graphics Adapter option ROM) provides a means for
  legacy x86 software to communicate with an attached serial console as
--- a/pc-bios/slof.bin
+++ b/pc-bios/slof.bin
--- a/roms/SLOF
+++ b/roms/SLOF
@ -1 +1 @@
-Subproject commit 8e012d6fddb62be833d746cef3f03e6c8beecde0
+Subproject commit e18ddad8516ff2cfe36ec130200318f7251aa78c