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hw/timer/imx_epit: define SR_OCIF

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Axel Heider 2022-11-19 15:59:40 +01:00 committed by Peter Maydell
parent 018ee7948f
commit 1ead962edf
2 changed files with 8 additions and 6 deletions
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12
hw/timer/imx_epit.c
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@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] = {
*/
static void imx_epit_update_int(IMXEPITState *s)
{
if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
break;
case 1: /* SR - ACK*/
/* writing 1 to OCIF clears the OCIF bit */
if (value & 0x01) {
s->sr = 0;
/* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
if (value & SR_OCIF) {
s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
imx_epit_update_int(s);
}
break;
@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque)
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("sr was %d\n", s->sr);
s->sr = 1;
/* Set interrupt status bit SR.OCIF and update the interrupt state */
s->sr |= SR_OCIF;
imx_epit_update_int(s);
}

2
include/hw/timer/imx_epit.h
View File

@ -53,6 +53,8 @@
#define CR_CLKSRC_SHIFT (24)
#define CR_CLKSRC_BITS (2)
#define SR_OCIF (1 << 0)
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
#define TYPE_IMX_EPIT "imx.epit"