target-arm: Suppress TBI for S2 translations
Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -6370,7 +6370,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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if (arm_el_is_aa64(env, el)) {
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if (arm_el_is_aa64(env, el)) {
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va_size = 64;
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va_size = 64;
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if (el > 1) {
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if (el > 1) {
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tbi = extract64(tcr->raw_tcr, 20, 1);
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if (mmu_idx != ARMMMUIdx_S2NS) {
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tbi = extract64(tcr->raw_tcr, 20, 1);
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}
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} else {
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} else {
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if (extract64(address, 55, 1)) {
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if (extract64(address, 55, 1)) {
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tbi = extract64(tcr->raw_tcr, 38, 1);
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tbi = extract64(tcr->raw_tcr, 38, 1);
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