Patch queue for s390 - 2015-05-13
A few TCG fixes for the s390x target. Nothing special, but with these applied I can run most of the SLE12 binaries in Linux-user emulation. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iQIcBAABAgAGBQJVU0hVAAoJECszeR4D/txgMdMQAKB9mN26EYtzFSCmKWiud4PF IHMpTWcuLTWCJOL2dtRLHTzN3QJdFk/Kg8snwJSulF26mcV+poYXLG/a8kbECFL/ iwoodw3lb4m3yU0QaXZcMDazWk1U1muXWMyjtuiutDePEqVf6YfP4iX2r6GKKVxq OQ0Nm5iirOCaP7CZMyseUmNNljTutOrx0xMwif8OKWrw8SPjIIgMSkVowAp5sBb7 c/DHYt1TNYfapOoFSVC06UU5GA5gsIyrNGj4EBMs+IpKmRVMiRTRa817liLE7Cjl p4lIqBPoBL3ccPamNASKqw+9CNEIWu6pIQw/uUhxlK6IwBwJZLMY6c0s47mAGBn4 ABeB5SODBy9LoQLcGJAFAKHLk1BUys2+AckXZXrkb0+T8tyuiugAsb72ynSqxkHo OfGh9OYGVIrm2+JSFdBkpbvYSdqbkj8fVUNHSTKpJVUNEJZzcFPFKOia9N6NKUEE HdA/D78GuYnQr+5hGvG9Mg3LPSl7OjeoMHKDFUMsBC/XYQOLQzURDxj709dO6ZkH vRTMVHyJ5LDHOzA4fk0TNRI6k/HUmYnAxK0rBHt25Q4TIMWBaARIMC5TPdl7DoIH ngG0wtHh8EJmJJi5afHjlsBnSGCMD06xNwrxha3jE8I7OwvmCwvIC7J4DMLgNPzi oUNYyBdQ6gNoJ7zSQrBZ =hVj1 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/agraf/tags/signed-s390-for-upstream' into staging Patch queue for s390 - 2015-05-13 A few TCG fixes for the s390x target. Nothing special, but with these applied I can run most of the SLE12 binaries in Linux-user emulation. # gpg: Signature made Wed May 13 13:49:25 2015 BST using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" * remotes/agraf/tags/signed-s390-for-upstream: s390x: Add interlocked access facility 1 instructions s390x: Add some documentation in opcode list s390x: Fix stoc direction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
1eeace9c23
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@ -1,3 +1,24 @@
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/*
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* Arguments to the opcode prototypes
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*
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* C(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC)
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* D(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC, DATA)
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*
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* OPC = (op << 8) | op2 where op is the major, op2 the minor opcode
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* NAME = name of the opcode, used internally
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* FMT = format of the opcode (defined in insn-format.def)
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* FAC = facility the opcode is available in (defined in DisasFacility)
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* I1 = func in1_xx fills o->in1
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* I2 = func in2_xx fills o->in2
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* P = func prep_xx initializes o->*out*
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* W = func wout_xx writes o->*out* somewhere
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* OP = func op_xx does the bulk of the operation
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* CC = func cout_xx defines how cc should get set
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* DATA = immediate argument to op_xx function
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*
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* The helpers get called in order: I1, I2, P, OP, W, CC
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*/
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/* ADD */
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C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
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C(0xb9f8, ARK, RRF_a, DO, r2, r3, new, r1_32, add, adds32)
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@ -338,6 +359,21 @@
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C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
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/* LOAD ADDRESS RELATIVE LONG */
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C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0)
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/* LOAD AND ADD */
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C(0xebf8, LAA, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, add, adds32)
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C(0xebe8, LAAG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, add, adds64)
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/* LOAD AND ADD LOGICAL */
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C(0xebfa, LAAL, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, add, addu32)
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C(0xebea, LAALG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, add, addu64)
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/* LOAD AND AND */
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C(0xebf4, LAN, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, and, nz32)
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C(0xebe4, LANG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, and, nz64)
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/* LOAD AND EXCLUSIVE OR */
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C(0xebf7, LAX, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, xor, nz32)
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C(0xebe7, LAXG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, xor, nz64)
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/* LOAD AND OR */
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C(0xebf6, LAO, RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, or, nz32)
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C(0xebe6, LAOG, RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, or, nz64)
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/* LOAD AND TEST */
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C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32)
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C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64)
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@ -417,6 +453,7 @@
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C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
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C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
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C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
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/* LOAD PAIR DISJOINT TODO */
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/* LOAD POSITIVE */
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C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32)
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C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64)
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@ -1118,6 +1118,7 @@ typedef enum DisasFacility {
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FAC_PC, /* population count */
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FAC_SCF, /* store clock fast */
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FAC_SFLE, /* store facility list extended */
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FAC_ILA, /* interlocked access facility 1 */
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} DisasFacility;
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struct DisasInsn {
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@ -3082,6 +3083,10 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
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disas_jcc(s, &c, get_field(s->fields, m3));
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/* We want to store when the condition is fulfilled, so branch
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out when it's not */
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c.cond = tcg_invert_cond(c.cond);
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lab = gen_new_label();
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if (c.is_64) {
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tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
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@ -4061,6 +4066,22 @@ static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
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}
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#define SPEC_wout_m2_32 0
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static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
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{
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/* XXX release reservation */
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tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
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store_reg32_i64(get_field(f, r1), o->in2);
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}
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#define SPEC_wout_m2_32_r1_atomic 0
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static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
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{
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/* XXX release reservation */
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tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
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store_reg(get_field(f, r1), o->in2);
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}
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#define SPEC_wout_m2_64_r1_atomic 0
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/* ====================================================================== */
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/* The "INput 1" generators. These load the first operand to an insn. */
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@ -4482,6 +4503,24 @@ static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
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}
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#define SPEC_in2_mri2_64 0
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static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
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{
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/* XXX should reserve the address */
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in1_la2(s, f, o);
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o->in2 = tcg_temp_new_i64();
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tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s));
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}
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#define SPEC_in2_m2_32s_atomic 0
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static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
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{
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/* XXX should reserve the address */
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in1_la2(s, f, o);
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o->in2 = tcg_temp_new_i64();
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tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s));
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}
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#define SPEC_in2_m2_64_atomic 0
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static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
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{
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o->in2 = tcg_const_i64(get_field(f, i2));
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