PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -392,6 +392,19 @@ typedef enum {
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/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
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/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
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#define CTRL_RUN PPC_BIT(63)
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#define CTRL_RUN PPC_BIT(63)
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/* EBB/BESCR bits */
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/* Global Enable */
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#define BESCR_GE PPC_BIT(0)
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/* External Event-based Exception Enable */
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#define BESCR_EE PPC_BIT(30)
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/* Performance Monitor Event-based Exception Enable */
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#define BESCR_PME PPC_BIT(31)
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/* External Event-based Exception Occurred */
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#define BESCR_EEO PPC_BIT(62)
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/* Performance Monitor Event-based Exception Occurred */
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#define BESCR_PMEO PPC_BIT(63)
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#define BESCR_INVALID PPC_BITMASK(32, 33)
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/* LPCR bits */
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/* LPCR bits */
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#define LPCR_VPM0 PPC_BIT(0)
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#define LPCR_VPM0 PPC_BIT(0)
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#define LPCR_VPM1 PPC_BIT(1)
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#define LPCR_VPM1 PPC_BIT(1)
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@ -1228,6 +1228,37 @@ void helper_hrfid(CPUPPCState *env)
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}
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}
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#endif
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#endif
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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void helper_rfebb(CPUPPCState *env, target_ulong s)
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{
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target_ulong msr = env->msr;
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/*
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* Handling of BESCR bits 32:33 according to PowerISA v3.1:
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*
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* "If BESCR 32:33 != 0b00 the instruction is treated as if
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* the instruction form were invalid."
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*/
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if (env->spr[SPR_BESCR] & BESCR_INVALID) {
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raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
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}
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env->nip = env->spr[SPR_EBBRR];
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/* Switching to 32-bit ? Crop the nip */
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if (!msr_is_64bit(env, msr)) {
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env->nip = (uint32_t)env->spr[SPR_EBBRR];
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}
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if (s) {
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env->spr[SPR_BESCR] |= BESCR_GE;
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} else {
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env->spr[SPR_BESCR] &= ~BESCR_GE;
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}
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}
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#endif
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/*****************************************************************************/
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/*****************************************************************************/
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/* Embedded PowerPC specific helpers */
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/* Embedded PowerPC specific helpers */
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void helper_40x_rfci(CPUPPCState *env)
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void helper_40x_rfci(CPUPPCState *env)
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@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32)
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DEF_HELPER_1(rfid, void, env)
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DEF_HELPER_1(rfid, void, env)
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DEF_HELPER_1(rfscv, void, env)
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DEF_HELPER_1(rfscv, void, env)
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DEF_HELPER_1(hrfid, void, env)
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DEF_HELPER_1(hrfid, void, env)
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DEF_HELPER_2(rfebb, void, env, tl)
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DEF_HELPER_2(store_lpcr, void, env, tl)
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DEF_HELPER_2(store_lpcr, void, env, tl)
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DEF_HELPER_2(store_pcr, void, env, tl)
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DEF_HELPER_2(store_pcr, void, env, tl)
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DEF_HELPER_2(store_mmcr0, void, env, tl)
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DEF_HELPER_2(store_mmcr0, void, env, tl)
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@ -470,3 +470,8 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
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## VSX Binary Floating-Point Convert Instructions
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## VSX Binary Floating-Point Convert Instructions
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XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
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XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
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### rfebb
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&XL_s s:uint8_t
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@XL_s ......-------------- s:1 .......... - &XL_s
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RFEBB 010011-------------- . 0010010010 - @XL_s
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@ -7461,6 +7461,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
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#include "translate/spe-impl.c.inc"
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#include "translate/spe-impl.c.inc"
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#include "translate/branch-impl.c.inc"
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/* Handles lfdp, lxsd, lxssp */
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/* Handles lfdp, lxsd, lxssp */
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static void gen_dform39(DisasContext *ctx)
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static void gen_dform39(DisasContext *ctx)
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{
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{
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@ -0,0 +1,33 @@
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/*
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* Power ISA decode for branch instructions
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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gen_icount_io_start(ctx);
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gen_update_cfar(ctx, ctx->cia);
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gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
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ctx->base.is_jmp = DISAS_CHAIN;
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return true;
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}
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#else
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static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
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{
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gen_invalid(ctx);
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return true;
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}
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#endif
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