target/arm: Move get_phys_addr_pmsav7 to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7d2e08c960
commit
1f2e87e5ab
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@ -11678,8 +11678,7 @@ do_fault:
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return true;
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}
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static bool pmsav7_use_background_region(ARMCPU *cpu,
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ARMMMUIdx mmu_idx, bool is_user)
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bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user)
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{
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/* Return true if we should use the default memory map as a
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* "background" region if there are no hits against any MPU regions.
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@ -11698,14 +11697,14 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
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}
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}
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static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
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bool m_is_ppb_region(CPUARMState *env, uint32_t address)
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{
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/* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
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return arm_feature(env, ARM_FEATURE_M) &&
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extract32(address, 20, 12) == 0xe00;
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}
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static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
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bool m_is_system_region(CPUARMState *env, uint32_t address)
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{
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/* True if address is in the M profile system region
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* 0xe0000000 - 0xffffffff
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@ -11713,193 +11712,6 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
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return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
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}
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bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = env_archcpu(env);
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int n;
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bool is_user = regime_is_user(env, mmu_idx);
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*phys_ptr = address;
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*page_size = TARGET_PAGE_SIZE;
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*prot = 0;
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if (regime_translation_disabled(env, mmu_idx) ||
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m_is_ppb_region(env, address)) {
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/* MPU disabled or M profile PPB access: use default memory map.
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* The other case which uses the default memory map in the
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* v7M ARM ARM pseudocode is exception vector reads from the vector
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* table. In QEMU those accesses are done in arm_v7m_load_vector(),
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* which always does a direct read using address_space_ldl(), rather
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* than going via this function, so we don't need to check that here.
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*/
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else { /* MPU enabled */
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for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
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/* region search */
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uint32_t base = env->pmsav7.drbar[n];
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uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
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uint32_t rmask;
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bool srdis = false;
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if (!(env->pmsav7.drsr[n] & 0x1)) {
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continue;
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}
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if (!rsize) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRSR[%d]: Rsize field cannot be 0\n", n);
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continue;
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}
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rsize++;
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rmask = (1ull << rsize) - 1;
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if (base & rmask) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRBAR[%d]: 0x%" PRIx32 " misaligned "
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"to DRSR region size, mask = 0x%" PRIx32 "\n",
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n, base, rmask);
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continue;
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}
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if (address < base || address > base + rmask) {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result in
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* incorrect TLB hits for subsequent accesses to addresses that
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* are in this MPU region.
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*/
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if (ranges_overlap(base, rmask,
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address & TARGET_PAGE_MASK,
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TARGET_PAGE_SIZE)) {
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*page_size = 1;
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}
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continue;
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}
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/* Region matched */
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if (rsize >= 8) { /* no subregions for regions < 256 bytes */
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int i, snd;
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uint32_t srdis_mask;
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rsize -= 3; /* sub region size (power of 2) */
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snd = ((address - base) >> rsize) & 0x7;
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srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
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srdis_mask = srdis ? 0x3 : 0x0;
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for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
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/* This will check in groups of 2, 4 and then 8, whether
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* the subregion bits are consistent. rsize is incremented
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* back up to give the region size, considering consistent
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* adjacent subregions as one region. Stop testing if rsize
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* is already big enough for an entire QEMU page.
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*/
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int snd_rounded = snd & ~(i - 1);
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uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
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snd_rounded + 8, i);
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if (srdis_mask ^ srdis_multi) {
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break;
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}
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srdis_mask = (srdis_mask << i) | srdis_mask;
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rsize++;
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}
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}
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if (srdis) {
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continue;
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}
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if (rsize < TARGET_PAGE_BITS) {
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*page_size = 1 << rsize;
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}
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break;
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}
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if (n == -1) { /* no hits */
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if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
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/* background fault */
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fi->type = ARMFault_Background;
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return true;
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}
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else { /* a MPU hit! */
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uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
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uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
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if (m_is_system_region(env, address)) {
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/* System space is always execute never */
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xn = 1;
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}
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if (is_user) { /* User mode AP bit decoding */
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switch (ap) {
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case 0:
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case 1:
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case 5:
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break; /* no access */
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case 3:
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*prot |= PAGE_WRITE;
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/* fall through */
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case 2:
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case 6:
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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case 7:
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/* for v7M, same as 6; for R profile a reserved value */
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if (arm_feature(env, ARM_FEATURE_M)) {
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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}
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/* fall through */
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRACR[%d]: Bad value for AP bits: 0x%"
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PRIx32 "\n", n, ap);
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}
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} else { /* Priv. mode AP bits decoding */
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switch (ap) {
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case 0:
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break; /* no access */
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case 1:
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case 2:
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case 3:
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*prot |= PAGE_WRITE;
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/* fall through */
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case 5:
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case 6:
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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case 7:
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/* for v7M, same as 6; for R profile a reserved value */
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if (arm_feature(env, ARM_FEATURE_M)) {
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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}
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/* fall through */
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRACR[%d]: Bad value for AP bits: 0x%"
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PRIx32 "\n", n, ap);
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}
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}
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/* execute never */
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if (xn) {
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*prot &= ~PAGE_EXEC;
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}
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}
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}
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return !(*prot & (1 << access_type));
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}
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static bool v8m_is_sau_exempt(CPUARMState *env,
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uint32_t address, MMUAccessType access_type)
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{
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190
target/arm/ptw.c
190
target/arm/ptw.c
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@ -8,6 +8,7 @@
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/range.h"
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#include "cpu.h"
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#include "internals.h"
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#include "ptw.h"
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@ -415,6 +416,195 @@ void get_phys_addr_pmsav7_default(CPUARMState *env,
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}
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}
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static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = env_archcpu(env);
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int n;
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bool is_user = regime_is_user(env, mmu_idx);
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*phys_ptr = address;
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*page_size = TARGET_PAGE_SIZE;
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*prot = 0;
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if (regime_translation_disabled(env, mmu_idx) ||
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m_is_ppb_region(env, address)) {
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/*
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* MPU disabled or M profile PPB access: use default memory map.
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* The other case which uses the default memory map in the
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* v7M ARM ARM pseudocode is exception vector reads from the vector
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* table. In QEMU those accesses are done in arm_v7m_load_vector(),
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* which always does a direct read using address_space_ldl(), rather
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* than going via this function, so we don't need to check that here.
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*/
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else { /* MPU enabled */
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for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
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/* region search */
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uint32_t base = env->pmsav7.drbar[n];
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uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
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uint32_t rmask;
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bool srdis = false;
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if (!(env->pmsav7.drsr[n] & 0x1)) {
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continue;
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}
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if (!rsize) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRSR[%d]: Rsize field cannot be 0\n", n);
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continue;
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}
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rsize++;
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rmask = (1ull << rsize) - 1;
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if (base & rmask) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRBAR[%d]: 0x%" PRIx32 " misaligned "
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"to DRSR region size, mask = 0x%" PRIx32 "\n",
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n, base, rmask);
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continue;
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}
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if (address < base || address > base + rmask) {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result in
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* incorrect TLB hits for subsequent accesses to addresses that
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* are in this MPU region.
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*/
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if (ranges_overlap(base, rmask,
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address & TARGET_PAGE_MASK,
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TARGET_PAGE_SIZE)) {
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*page_size = 1;
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}
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continue;
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}
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/* Region matched */
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if (rsize >= 8) { /* no subregions for regions < 256 bytes */
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int i, snd;
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uint32_t srdis_mask;
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rsize -= 3; /* sub region size (power of 2) */
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snd = ((address - base) >> rsize) & 0x7;
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srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
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srdis_mask = srdis ? 0x3 : 0x0;
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for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
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/*
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* This will check in groups of 2, 4 and then 8, whether
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* the subregion bits are consistent. rsize is incremented
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* back up to give the region size, considering consistent
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* adjacent subregions as one region. Stop testing if rsize
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* is already big enough for an entire QEMU page.
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*/
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int snd_rounded = snd & ~(i - 1);
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uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
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snd_rounded + 8, i);
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if (srdis_mask ^ srdis_multi) {
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break;
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}
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srdis_mask = (srdis_mask << i) | srdis_mask;
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rsize++;
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}
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}
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if (srdis) {
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continue;
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}
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if (rsize < TARGET_PAGE_BITS) {
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*page_size = 1 << rsize;
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}
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break;
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}
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if (n == -1) { /* no hits */
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if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
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/* background fault */
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fi->type = ARMFault_Background;
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return true;
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}
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else { /* a MPU hit! */
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uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
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uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
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if (m_is_system_region(env, address)) {
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/* System space is always execute never */
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xn = 1;
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}
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if (is_user) { /* User mode AP bit decoding */
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switch (ap) {
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case 0:
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case 1:
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case 5:
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break; /* no access */
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case 3:
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*prot |= PAGE_WRITE;
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/* fall through */
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case 2:
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case 6:
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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case 7:
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/* for v7M, same as 6; for R profile a reserved value */
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if (arm_feature(env, ARM_FEATURE_M)) {
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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}
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/* fall through */
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRACR[%d]: Bad value for AP bits: 0x%"
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PRIx32 "\n", n, ap);
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}
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} else { /* Priv. mode AP bits decoding */
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switch (ap) {
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case 0:
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break; /* no access */
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case 1:
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case 2:
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case 3:
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*prot |= PAGE_WRITE;
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/* fall through */
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case 5:
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case 6:
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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case 7:
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/* for v7M, same as 6; for R profile a reserved value */
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if (arm_feature(env, ARM_FEATURE_M)) {
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*prot |= PAGE_READ | PAGE_EXEC;
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break;
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}
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/* fall through */
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"DRACR[%d]: Bad value for AP bits: 0x%"
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PRIx32 "\n", n, ap);
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}
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}
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/* execute never */
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if (xn) {
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*prot &= ~PAGE_EXEC;
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}
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}
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}
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fi->type = ARMFault_Permission;
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fi->level = 1;
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return !(*prot & (1 << access_type));
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}
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/**
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* get_phys_addr - get the physical address for this virtual address
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*
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@ -33,14 +33,14 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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bool m_is_ppb_region(CPUARMState *env, uint32_t address);
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bool m_is_system_region(CPUARMState *env, uint32_t address);
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void get_phys_addr_pmsav7_default(CPUARMState *env,
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ARMMMUIdx mmu_idx,
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int32_t address, int *prot);
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bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi);
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bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user);
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bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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