diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 4072abe3e4..9c6c109327 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,20 @@
obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
+decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+
+target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/decode_insn16.inc.c: \
+ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+ $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+ target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
new file mode 100644
index 0000000000..17cc52cf2a
--- /dev/null
+++ b/target/riscv/insn16.decode
@@ -0,0 +1,129 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see .
+
+# Fields:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
+
+# Immediates:
+%imm_ci 12:s1 2:5
+%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
+%uimm_cl_d 5:2 10:3 !function=ex_shift_3
+%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
+%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+%nzuimm_6bit 12:1 2:5
+%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
+%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
+
+%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
+%imm_lui 12:s1 2:5 !function=ex_shift_12
+
+
+
+# Argument sets:
+&cl rs1 rd
+&cl_dw uimm rs1 rd
+&ci imm rd
+&ciw nzuimm rd
+&cs rs1 rs2
+&cs_dw uimm rs1 rs2
+&cb imm rs1
+&cr rd rs2
+&cj imm
+&c_shift shamt rd
+
+&c_ld uimm rd
+&c_sd uimm rs2
+
+&caddi16sp_lui imm_lui imm_addi16sp rd
+&cflwsp_ldsp uimm_flwsp uimm_ldsp rd
+&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2
+
+# Formats 16:
+@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
+@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
+@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
+@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
+@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
+@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
+@cj ... ........... .. &cj imm=%imm_cj
+
+@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
+@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
+@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
+@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
+
+@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
+@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+ uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
+ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
+
+@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
+
+@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+c_addi4spn 000 ........ ... 00 @ciw
+c_fld 001 ... ... .. ... 00 @cl_d
+c_lw 010 ... ... .. ... 00 @cl_w
+c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
+c_fsd 101 ... ... .. ... 00 @cs_d
+c_sw 110 ... ... .. ... 00 @cs_w
+c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+c_addi 000 . ..... ..... 01 @ci
+c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
+c_li 010 . ..... ..... 01 @ci
+c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
+c_srli 100 . 00 ... ..... 01 @c_shift
+c_srai 100 . 01 ... ..... 01 @c_shift
+c_andi 100 . 10 ... ..... 01 @c_andi
+c_sub 100 0 11 ... 00 ... 01 @cs_2
+c_xor 100 0 11 ... 01 ... 01 @cs_2
+c_or 100 0 11 ... 10 ... 01 @cs_2
+c_and 100 0 11 ... 11 ... 01 @cs_2
+c_subw 100 1 11 ... 00 ... 01 @cs_2
+c_addw 100 1 11 ... 01 ... 01 @cs_2
+c_j 101 ........... 01 @cj
+c_beqz 110 ... ... ..... 01 @cb
+c_bnez 111 ... ... ..... 01 @cb
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+c_slli 000 . ..... ..... 10 @c_shift2
+c_fldsp 001 . ..... ..... 10 @c_ld
+c_lwsp 010 . ..... ..... 10 @c_lw
+c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
+c_jr_mv 100 0 ..... ..... 10 @cr
+c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
+c_fsdsp 101 ...... ..... 10 @c_sd
+c_swsp 110 . ..... ..... 10 @c_sw
+c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
new file mode 100644
index 0000000000..380bf791bc
--- /dev/null
+++ b/target/riscv/insn32-64.decode
@@ -0,0 +1,72 @@
+#
+# RISC-V translation routines for the RV Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see .
+
+# This is concatenated with insn32.decode for risc64 targets.
+# Most of the fields and formats are there.
+
+%sh5 20:5
+
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu ............ ..... 110 ..... 0000011 @i
+ld ............ ..... 011 ..... 0000011 @i
+sd ....... ..... ..... 011 ..... 0100011 @s
+addiw ............ ..... 000 ..... 0011011 @i
+slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
+srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
+sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
+addw 0000000 ..... ..... 000 ..... 0111011 @r
+subw 0100000 ..... ..... 000 ..... 0111011 @r
+sllw 0000000 ..... ..... 001 ..... 0111011 @r
+srlw 0000000 ..... ..... 101 ..... 0111011 @r
+sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
new file mode 100644
index 0000000000..6f3ab7aa52
--- /dev/null
+++ b/target/riscv/insn32.decode
@@ -0,0 +1,201 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see .
+
+# Fields:
+%rs3 27:5
+%rs2 20:5
+%rs1 15:5
+%rd 7:5
+
+%sh10 20:10
+%csr 20:12
+%rm 12:3
+
+# immediates:
+%imm_i 20:s12
+%imm_s 25:s7 7:5
+%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
+%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
+%imm_u 12:s20 !function=ex_shift_12
+
+# Argument sets:
+&b imm rs2 rs1
+&i imm rs1 rd
+&r rd rs1 rs2
+&shift shamt rs1 rd
+&atomic aq rl rs2 rs1 rd
+
+# Formats 32:
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
+@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
+@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
+@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
+@u .................... ..... ....... imm=%imm_u %rd
+@j .................... ..... ....... imm=%imm_j %rd
+
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@csr ............ ..... ... ..... ....... %csr %rs1 %rd
+
+@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
+@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
+
+@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
+@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
+@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
+@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+
+@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+
+
+# *** Privileged Instructions ***
+ecall 000000000000 00000 000 00000 1110011
+ebreak 000000000001 00000 000 00000 1110011
+uret 0000000 00010 00000 000 00000 1110011
+sret 0001000 00010 00000 000 00000 1110011
+hret 0010000 00010 00000 000 00000 1110011
+mret 0011000 00010 00000 000 00000 1110011
+wfi 0001000 00101 00000 000 00000 1110011
+sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+
+# *** RV32I Base Instruction Set ***
+lui .................... ..... 0110111 @u
+auipc .................... ..... 0010111 @u
+jal .................... ..... 1101111 @j
+jalr ............ ..... 000 ..... 1100111 @i
+beq ....... ..... ..... 000 ..... 1100011 @b
+bne ....... ..... ..... 001 ..... 1100011 @b
+blt ....... ..... ..... 100 ..... 1100011 @b
+bge ....... ..... ..... 101 ..... 1100011 @b
+bltu ....... ..... ..... 110 ..... 1100011 @b
+bgeu ....... ..... ..... 111 ..... 1100011 @b
+lb ............ ..... 000 ..... 0000011 @i
+lh ............ ..... 001 ..... 0000011 @i
+lw ............ ..... 010 ..... 0000011 @i
+lbu ............ ..... 100 ..... 0000011 @i
+lhu ............ ..... 101 ..... 0000011 @i
+sb ....... ..... ..... 000 ..... 0100011 @s
+sh ....... ..... ..... 001 ..... 0100011 @s
+sw ....... ..... ..... 010 ..... 0100011 @s
+addi ............ ..... 000 ..... 0010011 @i
+slti ............ ..... 010 ..... 0010011 @i
+sltiu ............ ..... 011 ..... 0010011 @i
+xori ............ ..... 100 ..... 0010011 @i
+ori ............ ..... 110 ..... 0010011 @i
+andi ............ ..... 111 ..... 0010011 @i
+slli 00.... ...... ..... 001 ..... 0010011 @sh
+srli 00.... ...... ..... 101 ..... 0010011 @sh
+srai 01.... ...... ..... 101 ..... 0010011 @sh
+add 0000000 ..... ..... 000 ..... 0110011 @r
+sub 0100000 ..... ..... 000 ..... 0110011 @r
+sll 0000000 ..... ..... 001 ..... 0110011 @r
+slt 0000000 ..... ..... 010 ..... 0110011 @r
+sltu 0000000 ..... ..... 011 ..... 0110011 @r
+xor 0000000 ..... ..... 100 ..... 0110011 @r
+srl 0000000 ..... ..... 101 ..... 0110011 @r
+sra 0100000 ..... ..... 101 ..... 0110011 @r
+or 0000000 ..... ..... 110 ..... 0110011 @r
+and 0000000 ..... ..... 111 ..... 0110011 @r
+fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+fence_i ---- ---- ---- ----- 001 ----- 0001111
+csrrw ............ ..... 001 ..... 1110011 @csr
+csrrs ............ ..... 010 ..... 1110011 @csr
+csrrc ............ ..... 011 ..... 1110011 @csr
+csrrwi ............ ..... 101 ..... 1110011 @csr
+csrrsi ............ ..... 110 ..... 1110011 @csr
+csrrci ............ ..... 111 ..... 1110011 @csr
+
+# *** RV32M Standard Extension ***
+mul 0000001 ..... ..... 000 ..... 0110011 @r
+mulh 0000001 ..... ..... 001 ..... 0110011 @r
+mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
+mulhu 0000001 ..... ..... 011 ..... 0110011 @r
+div 0000001 ..... ..... 100 ..... 0110011 @r
+divu 0000001 ..... ..... 101 ..... 0110011 @r
+rem 0000001 ..... ..... 110 ..... 0110011 @r
+remu 0000001 ..... ..... 111 ..... 0110011 @r
+
+# *** RV32A Standard Extension ***
+lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
+sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
+amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
+amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
+amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
+amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
+amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
+amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
+
+# *** RV32F Standard Extension ***
+flw ............ ..... 010 ..... 0000111 @i
+fsw ....... ..... ..... 010 ..... 0100111 @s
+fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
+fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
+fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
+fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
+fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
+fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
+fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
+fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
+fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
+fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
+feq_s 1010000 ..... ..... 010 ..... 1010011 @r
+flt_s 1010000 ..... ..... 001 ..... 1010011 @r
+fle_s 1010000 ..... ..... 000 ..... 1010011 @r
+fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
+fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
+fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32D Standard Extension ***
+fld ............ ..... 011 ..... 0000111 @i
+fsd ....... ..... ..... 011 ..... 0100111 @s
+fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
+fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
+fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
+fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
+fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
+fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
+fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
+fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
+fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
+fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
+feq_d 1010001 ..... ..... 010 ..... 1010011 @r
+flt_d 1010001 ..... ..... 001 ..... 1010011 @r
+fle_d 1010001 ..... ..... 000 ..... 1010011 @r
+fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
+fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index 0000000000..acb605923e
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,110 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+ /* always generates U-level ECALL, fixed in do_interrupt handler */
+ generate_exception(ctx, RISCV_EXCP_U_ECALL);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+ generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+ return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+ if (has_ext(ctx, RVS)) {
+ gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ return false;
+ }
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a)
+{
+ return false;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ gen_helper_wfi(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ }
+#endif
+ return false;
+}
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
new file mode 100644
index 0000000000..f6dbbc065e
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -0,0 +1,218 @@
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ /* Put addr in load_res, data in load_val. */
+ gen_get_gpr(src1, a->rs1);
+ if (a->rl) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+ tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+ if (a->aq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ tcg_gen_mov_tl(load_res, src1);
+ gen_set_gpr(a->rd, load_val);
+
+ tcg_temp_free(src1);
+ return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+ gen_get_gpr(src2, a->rs2);
+ /*
+ * Note that the TCG atomic primitives are SC,
+ * so we can ignore AQ/RL along this path.
+ */
+ tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+ gen_set_gpr(a->rd, dat);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ /*
+ * Address comparion failure. However, we still need to
+ * provide the memory barrier implied by AQ/RL.
+ */
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ tcg_gen_movi_tl(dat, 1);
+ gen_set_gpr(a->rd, dat);
+
+ gen_set_label(l2);
+ tcg_temp_free(dat);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),
+ TCGMemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+
+ (*func)(src2, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(a->rd, src2);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
new file mode 100644
index 0000000000..bcdf64d3b7
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -0,0 +1,327 @@
+/*
+ * RISC-V translation routines for the RVC Compressed Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
+{
+ if (a->nzuimm == 0) {
+ /* Reserved in ISA */
+ return false;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.LD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
+{
+ arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
+{
+ arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSW ( RV32FC-only ) */
+ return false;
+#else
+ /* C.SD ( RV64C/RV128C-only ) */
+ return false;
+#endif
+}
+
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
+{
+ if (a->imm == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.JAL */
+ arg_jal arg = { .rd = 1, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+#else
+ /* C.ADDIW */
+ arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_addiw(ctx, &arg);
+#endif
+}
+
+static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
+{
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
+ return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
+{
+ if (a->rd == 2) {
+ /* C.ADDI16SP */
+ arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
+ return trans_addi(ctx, &arg);
+ } else if (a->imm_lui != 0) {
+ /* C.LUI */
+ if (a->rd == 0) {
+ /* Hint: insn is valid but does not affect state */
+ return true;
+ }
+ arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
+ return trans_lui(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srli(ctx, &arg);
+}
+
+static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_srai(ctx, &arg);
+}
+
+static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
+{
+ arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+ return trans_andi(ctx, &arg);
+}
+
+static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
+{
+ arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_sub(ctx, &arg);
+}
+
+static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
+{
+ arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_xor(ctx, &arg);
+}
+
+static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
+{
+ arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_or(ctx, &arg);
+}
+
+static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
+{
+ arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_and(ctx, &arg);
+}
+
+static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_subw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
+{
+#ifdef TARGET_RISCV64
+ arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_addw(ctx, &arg);
+#else
+ return false;
+#endif
+}
+
+static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
+{
+ arg_jal arg = { .rd = 0, .imm = a->imm };
+ return trans_jal(ctx, &arg);
+}
+
+static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
+{
+ arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_beq(ctx, &arg);
+}
+
+static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
+{
+ arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
+ return trans_bne(ctx, &arg);
+}
+
+static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
+{
+ int shamt = a->shamt;
+ if (shamt == 0) {
+ /* For RV128 a shamt of 0 means a shift by 64 */
+ shamt = 64;
+ }
+ /* Ensure, that shamt[5] is zero for RV32 */
+ if (shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+ return trans_slli(ctx, &arg);
+}
+
+static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
+{
+ arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
+{
+ arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+ return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FLWSP */
+ arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
+ return trans_flw(ctx, &arg_flw);
+#else
+ /* C.LDSP */
+ arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
+ return trans_ld(ctx, &arg_ld);
+#endif
+ return false;
+}
+
+static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
+{
+ if (a->rd != 0 && a->rs2 == 0) {
+ /* C.JR */
+ arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else if (a->rd != 0 && a->rs2 != 0) {
+ /* C.MV */
+ arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ return false;
+}
+
+static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
+{
+ if (a->rd == 0 && a->rs2 == 0) {
+ /* C.EBREAK */
+ arg_ebreak arg = { };
+ return trans_ebreak(ctx, &arg);
+ } else if (a->rd != 0) {
+ if (a->rs2 == 0) {
+ /* C.JALR */
+ arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
+ return trans_jalr(ctx, &arg);
+ } else {
+ /* C.ADD */
+ arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
+ return trans_add(ctx, &arg);
+ }
+ }
+ return false;
+}
+
+static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
+{
+ arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_fsd(ctx, &arg);
+}
+
+static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
+{
+ arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
+ return trans_sw(ctx, &arg);
+}
+
+static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
+{
+#ifdef TARGET_RISCV32
+ /* C.FSWSP */
+ arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+ return trans_fsw(ctx, &a_fsw);
+#else
+ /* C.SDSP */
+ arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
+ return trans_sd(ctx, &a_sd);
+#endif
+}
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
new file mode 100644
index 0000000000..393fa0248c
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -0,0 +1,442 @@
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
+{
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
+ cpu_fpr[a->rs1], 0, 63);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+#endif
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
new file mode 100644
index 0000000000..172dbfa919
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -0,0 +1,439 @@
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+#define REQUIRE_FPU do {\
+ if (ctx->mstatus_fs == 0) \
+ return false; \
+} while (0)
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+ /* RISC-V requires NaN-boxing of narrower width floating point values */
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
+
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else { /* FSGNJ */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
+ 0, 31);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
+{
+ /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+
+ gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
+{
+ /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+#else
+ tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
+#endif
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
new file mode 100644
index 0000000000..d420a4d8b2
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -0,0 +1,568 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ }
+ return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ }
+ return true;
+}
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a)
+{
+ gen_jal(ctx, a->rd, a->imm);
+ return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+{
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!has_ext(ctx, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
+{
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+ return gen_branch(ctx, a, TCG_COND_NE);
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+ return gen_branch(ctx, a, TCG_COND_LT);
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+ return gen_branch(ctx, a, TCG_COND_GE);
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+ return gen_branch(ctx, a, TCG_COND_LTU);
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+ return gen_branch(ctx, a, TCG_COND_GEU);
+}
+
+static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ return true;
+}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ return gen_load(ctx, a, MO_SB);
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+ return gen_load(ctx, a, MO_TESW);
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+ return gen_load(ctx, a, MO_TESL);
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+ return gen_load(ctx, a, MO_UB);
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+ return gen_load(ctx, a, MO_TEUW);
+}
+
+static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ return true;
+}
+
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+ return gen_store(ctx, a, MO_TESW);
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+ return gen_store(ctx, a, MO_TESL);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ return gen_load(ctx, a, MO_TEQ);
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a)
+{
+ return gen_store(ctx, a, MO_TEQ);
+}
+#endif
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+ return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
+}
+
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
+
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ return gen_arith_imm(ctx, a, &gen_slt);
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
+{
+ return gen_arith_imm(ctx, a, &gen_sltu);
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a)
+{
+ return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a)
+{
+ return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a)
+{
+ return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_srli(DisasContext *ctx, arg_srli *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shri_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_srai(DisasContext *ctx, arg_srai *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_sari_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_add(DisasContext *ctx, arg_add *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
+}
+
+static bool trans_sub(DisasContext *ctx, arg_sub *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
+}
+
+static bool trans_sll(DisasContext *ctx, arg_sll *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
+}
+
+static bool trans_slt(DisasContext *ctx, arg_slt *a)
+{
+ return gen_arith(ctx, a, &gen_slt);
+}
+
+static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
+{
+ return gen_arith(ctx, a, &gen_sltu);
+}
+
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
+}
+
+static bool trans_srl(DisasContext *ctx, arg_srl *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
+}
+
+static bool trans_sra(DisasContext *ctx, arg_sra *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
+}
+
+static bool trans_or(DisasContext *ctx, arg_or *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
+}
+
+static bool trans_and(DisasContext *ctx, arg_and *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
+{
+ return gen_arith_imm(ctx, a, &gen_addw);
+}
+
+static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+{
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+{
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+}
+
+static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+{
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+}
+
+static bool trans_addw(DisasContext *ctx, arg_addw *a)
+{
+ return gen_arith(ctx, a, &gen_addw);
+}
+
+static bool trans_subw(DisasContext *ctx, arg_subw *a)
+{
+ return gen_arith(ctx, a, &gen_subw);
+}
+
+static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
+ return true;
+}
+#endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+ /*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+#define RISCV_OP_CSR_PRE do {\
+ source1 = tcg_temp_new(); \
+ csr_store = tcg_temp_new(); \
+ dest = tcg_temp_new(); \
+ rs1_pass = tcg_temp_new(); \
+ gen_get_gpr(source1, a->rs1); \
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+ tcg_gen_movi_tl(rs1_pass, a->rs1); \
+ tcg_gen_movi_tl(csr_store, a->csr); \
+ gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+ gen_io_end(); \
+ gen_set_gpr(a->rd, dest); \
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+ tcg_gen_exit_tb(NULL, 0); \
+ ctx->base.is_jmp = DISAS_NORETURN; \
+ tcg_temp_free(source1); \
+ tcg_temp_free(csr_store); \
+ tcg_temp_free(dest); \
+ tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 0000000000..204af225f8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,120 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_mulhsu);
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_div);
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_divu);
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_rem);
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_remu);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_mulw);
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_div);
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_divu);
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_rem);
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_remu);
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b7176cbf98..049fa65c66 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
int frm;
} DisasContext;
+#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
@@ -69,6 +70,7 @@ static const int tcg_memop_lookup[8] = {
[6] = MO_TEUL,
#endif
};
+#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
@@ -186,367 +188,112 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
- uint32_t rs2, int rm, uint64_t min)
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
- switch (rm) {
- case 0: /* fsgnj */
- if (rs1 == rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- }
- break;
- case 1: /* fsgnjn */
- if (rs1 == rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[rs2]);
- tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- tcg_temp_free_i64(t0);
- }
- break;
- case 2: /* fsgnjx */
- if (rs1 == rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
- tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
- tcg_temp_free_i64(t0);
- }
- break;
- default:
- gen_exception_illegal(ctx);
- }
+ TCGv cond1, cond2, zeroreg, resultopt1;
+ /*
+ * Handle by altering args to tcg_gen_div to produce req'd results:
+ * For overflow: want source1 in source1 and 1 in source2
+ * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
+ */
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ ((target_ulong)1) << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
+ /* if div by zero, set source1 to -1, otherwise don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
+ resultopt1);
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond1, cond1, cond2);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_div_tl(ret, source1, source2);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
-static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int rs2)
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
- switch (opc) {
- CASE_OP_32_64(OPC_RISC_ADD):
- tcg_gen_add_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_SUB):
- tcg_gen_sub_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLW:
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SLL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
- case OPC_RISC_SLT:
- tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
- break;
- case OPC_RISC_SLTU:
- tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
- break;
- case OPC_RISC_XOR:
- tcg_gen_xor_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRLW:
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRAW:
- /* first, trick to get it to act like working on 32 bits (get rid of
- upper 32, sign extend to fill space) */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRA:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
- case OPC_RISC_OR:
- tcg_gen_or_tl(source1, source1, source2);
- break;
- case OPC_RISC_AND:
- tcg_gen_and_tl(source1, source1, source2);
- break;
- CASE_OP_32_64(OPC_RISC_MUL):
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_mul_tl(source1, source1, source2);
- break;
- case OPC_RISC_MULH:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_muls2_tl(source2, source1, source1, source2);
- break;
- case OPC_RISC_MULHSU:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- gen_mulhsu(source1, source1, source2);
- break;
- case OPC_RISC_MULHU:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVW:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to DIV */
-#endif
- case OPC_RISC_DIV:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- /* Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in source1 and 1 in source2
- * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- ((target_ulong)1) << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
- resultopt1);
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond1, cond1, cond2);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_div_tl(source1, source1, source2);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
+ resultopt1);
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_divu_tl(ret, source1, source2);
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_DIVUW:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to DIVU */
-#endif
- case OPC_RISC_DIVU:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
- resultopt1);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_divu_tl(source1, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMW:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
- /* fall through to REM */
-#endif
- case OPC_RISC_REM:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, 1L);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- (target_ulong)1 << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond2, cond1, cond2);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
- resultopt1);
- tcg_gen_rem_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_REMUW:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
- /* fall through to REMU */
-#endif
- case OPC_RISC_REMU:
- if (!has_ext(ctx, RVM)) {
- goto do_illegal;
- }
- cond1 = tcg_temp_new();
- zeroreg = tcg_const_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_remu_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(zeroreg);
- tcg_temp_free(resultopt1);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
+ TCGv cond1, cond2, zeroreg, resultopt1;
- gen_get_gpr(source1, rs1);
+ cond1 = tcg_temp_new();
+ cond2 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
+ tcg_gen_movi_tl(resultopt1, 1L);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
+ (target_ulong)1 << (TARGET_LONG_BITS - 1));
+ tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_or_tl(cond2, cond1, cond2);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
+ resultopt1);
+ tcg_gen_rem_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
+ tcg_temp_free(cond1);
+ tcg_temp_free(cond2);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
+}
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv cond1, zeroreg, resultopt1;
+ cond1 = tcg_temp_new();
+ zeroreg = tcg_const_tl(0);
+ resultopt1 = tcg_temp_new();
+
+ tcg_gen_movi_tl(resultopt1, (target_ulong)1);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
+ tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
+ resultopt1);
+ tcg_gen_remu_tl(resultopt1, source1, source2);
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
+ source1);
+
+ tcg_temp_free(cond1);
+ tcg_temp_free(zeroreg);
+ tcg_temp_free(resultopt1);
}
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
@@ -569,92 +316,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!has_ext(ctx, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
-static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+#ifdef TARGET_RISCV64
+static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -674,7 +337,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(t1);
}
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -693,6 +356,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(t0);
tcg_temp_free(dat);
}
+#endif
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
@@ -719,6 +383,7 @@ static void mark_fs_dirty(DisasContext *ctx)
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
+#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -793,143 +458,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
-
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int rs2)
-{
- TCGv src1, src2, dat;
- TCGLabel *l1, *l2;
- TCGMemOp mop;
- bool aq, rl;
-
- /* Extract the size of the atomic operation. */
- switch (extract32(opc, 12, 3)) {
- case 2: /* 32-bit */
- mop = MO_ALIGN | MO_TESL;
- break;
-#if defined(TARGET_RISCV64)
- case 3: /* 64-bit */
- mop = MO_ALIGN | MO_TEQ;
- break;
#endif
- default:
- gen_exception_illegal(ctx);
- return;
- }
- rl = extract32(opc, 25, 1);
- aq = extract32(opc, 26, 1);
-
- src1 = tcg_temp_new();
- src2 = tcg_temp_new();
-
- switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
- case OPC_RISC_LR:
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, rs1);
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(rd, load_val);
- break;
-
- case OPC_RISC_SC:
- l1 = gen_new_label();
- l2 = gen_new_label();
- dat = tcg_temp_new();
-
- gen_get_gpr(src1, rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, rs2);
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /* Address comparion failure. However, we still need to
- provide the memory barrier implied by AQ/RL. */
- tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(rd, dat);
-
- gen_set_label(l2);
- tcg_temp_free(dat);
- break;
-
- case OPC_RISC_AMOSWAP:
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOADD:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOXOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOAND:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMIN:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAX:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMINU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAXU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(src1);
- tcg_temp_free(src2);
-}
static void gen_set_rm(DisasContext *ctx, int rm)
{
@@ -944,659 +473,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rm)
-{
- TCGv t0 = NULL;
- bool fp_output = true;
-
- if (ctx->mstatus_fs == 0) {
- goto do_illegal;
- }
-
- switch (opc) {
- case OPC_RISC_FADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
- break;
-
- case OPC_RISC_FMIN_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- /* also handles: OPC_RISC_FMAX_S */
- switch (rm) {
- case 0x0:
- gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_S:
- /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0x0:
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x2:
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_W_S:
- /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0: /* FCVT_W_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1: /* FCVT_WU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_L_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3: /* FCVT_LU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_S_W:
- /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0: /* FCVT_S_W */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1: /* FCVT_S_WU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_S_L */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3: /* FCVT_S_LU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_S:
- /* also OPC_RISC_FCLASS_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0: /* FMV */
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
-#endif
- break;
- case 1:
- gen_helper_fclass_s(t0, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FMV_S_X:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
-#endif
- tcg_temp_free(t0);
- break;
-
- /* double */
- case OPC_RISC_FADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_D:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
- break;
-
- case OPC_RISC_FMIN_D:
- /* also OPC_RISC_FMAX_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rm) {
- case 0:
- gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_S_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rs2) {
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_D_S:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_D:
- /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0:
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 2:
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_W_D:
- /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_D_W:
- /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_D:
- /* also OPC_RISC_FCLASS_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rm) {
-#if defined(TARGET_RISCV64)
- case 0: /* FMV */
- gen_set_gpr(rd, cpu_fpr[rs1]);
- break;
-#endif
- case 1:
- t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[rs1]);
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
- default:
- goto do_illegal;
- }
- fp_output = false;
- break;
-
-#if defined(TARGET_RISCV64)
- case OPC_RISC_FMV_D_X:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_mov_tl(cpu_fpr[rd], t0);
- tcg_temp_free(t0);
- break;
-#endif
-
- default:
- do_illegal:
- if (t0) {
- tcg_temp_free(t0);
- }
- gen_exception_illegal(ctx);
- return;
- }
-
- if (fp_output) {
- mark_fs_dirty(ctx);
- }
-}
-
-static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int csr)
-{
- TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
- source1 = tcg_temp_new();
- csr_store = tcg_temp_new();
- dest = tcg_temp_new();
- rs1_pass = tcg_temp_new();
- imm_rs1 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- tcg_gen_movi_tl(rs1_pass, rs1);
- tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */
-
-#ifndef CONFIG_USER_ONLY
- /* Extract funct7 value and check whether it matches SFENCE.VMA */
- if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
- /* sfence.vma */
- /* TODO: handle ASID specific fences */
- gen_helper_tlb_flush(cpu_env);
- return;
- } else {
- gen_exception_illegal(ctx);
- }
- }
-#endif
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-#ifndef CONFIG_USER_ONLY
- case 0x002: /* URET */
- gen_exception_illegal(ctx);
- break;
- case 0x102: /* SRET */
- if (has_ext(ctx, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- gen_exception_illegal(ctx);
- }
- break;
- case 0x202: /* HRET */
- gen_exception_illegal(ctx);
- break;
- case 0x302: /* MRET */
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x7b2: /* DRET */
- gen_exception_illegal(ctx);
- break;
- case 0x105: /* WFI */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- gen_helper_wfi(cpu_env);
- break;
- case 0x104: /* SFENCE.VM */
- if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
- gen_helper_tlb_flush(cpu_env);
- } else {
- gen_exception_illegal(ctx);
- }
- break;
-#endif
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- default:
- tcg_gen_movi_tl(imm_rs1, rs1);
- gen_io_start();
- switch (opc) {
- case OPC_RISC_CSRRW:
- gen_helper_csrrw(dest, cpu_env, source1, csr_store);
- break;
- case OPC_RISC_CSRRS:
- gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRC:
- gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRWI:
- gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store);
- break;
- case OPC_RISC_CSRRSI:
- gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- case OPC_RISC_CSRRCI:
- gen_helper_csrrc(dest, cpu_env, imm_rs1, csr_store, rs1_pass);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- gen_io_end();
- gen_set_gpr(rd, dest);
- /* end tb since we may be changing priv modes, to get mmu_index right */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- }
- tcg_temp_free(source1);
- tcg_temp_free(csr_store);
- tcg_temp_free(dest);
- tcg_temp_free(rs1_pass);
- tcg_temp_free(imm_rs1);
-}
-
static void decode_RV32_64C0(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -1604,31 +480,10 @@ static void decode_RV32_64C0(DisasContext *ctx)
uint8_t rs1s = GET_C_RS1S(ctx->opcode);
switch (funct3) {
- case 0:
- /* illegal */
- if (ctx->opcode == 0) {
- gen_exception_illegal(ctx);
- } else {
- /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2,
- GET_C_ADDI4SPN_IMM(ctx->opcode));
- }
- break;
- case 1:
- /* C.FLD -> fld rd', offset[7:3](rs1')*/
- gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s,
- GET_C_LD_IMM(ctx->opcode));
- /* C.LQ(RV128) */
- break;
- case 2:
- /* C.LW -> lw rd', offset[6:2](rs1') */
- gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
- gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+ gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
@@ -1636,25 +491,10 @@ static void decode_RV32_64C0(DisasContext *ctx)
GET_C_LW_IMM(ctx->opcode));
#endif
break;
- case 4:
- /* reserved */
- gen_exception_illegal(ctx);
- break;
- case 5:
- /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */
- gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2,
- GET_C_LD_IMM(ctx->opcode));
- /* C.SQ (RV128) */
- break;
- case 6:
- /* C.SW -> sw rs2', offset[6:2](rs1')*/
- gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2,
- GET_C_LW_IMM(ctx->opcode));
- break;
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+ gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
@@ -1665,198 +505,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C1(DisasContext *ctx)
-{
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
- uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
- uint8_t rs1s, rs2s;
- uint8_t funct2;
-
- switch (funct3) {
- case 0:
- /* C.ADDI -> addi rd, rd, nzimm[5:0] */
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
- break;
- case 1:
-#if defined(TARGET_RISCV64)
- /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1,
- GET_C_IMM(ctx->opcode));
-#else
- /* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode));
-#endif
- break;
- case 2:
- /* C.LI -> addi rd, x0, imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode));
- break;
- case 3:
- if (rd_rs1 == 2) {
- /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/
- gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2,
- GET_C_ADDI16SP_IMM(ctx->opcode));
- } else if (rd_rs1 != 0) {
- /* C.LUI (rs1/rd =/= {0,2}) -> lui rd, nzimm[17:12]*/
- tcg_gen_movi_tl(cpu_gpr[rd_rs1],
- GET_C_IMM(ctx->opcode) << 12);
- }
- break;
- case 4:
- funct2 = extract32(ctx->opcode, 10, 2);
- rs1s = GET_C_RS1S(ctx->opcode);
- switch (funct2) {
- case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode));
- /* C.SRLI64(RV128) */
- break;
- case 1:
- /* C.SRAI -> srai rd', rd', shamt[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s,
- GET_C_ZIMM(ctx->opcode) | 0x400);
- /* C.SRAI64(RV128) */
- break;
- case 2:
- /* C.ANDI -> andi rd', rd', imm[5:0]*/
- gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s,
- GET_C_IMM(ctx->opcode));
- break;
- case 3:
- funct2 = extract32(ctx->opcode, 5, 2);
- rs2s = GET_C_RS2S(ctx->opcode);
- switch (funct2) {
- case 0:
- /* C.SUB -> sub rd', rd', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 1:
- /* C.XOR -> xor rs1', rs1', rs2' */
- if (extract32(ctx->opcode, 12, 1) == 0) {
- gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s);
- }
-#if defined(TARGET_RISCV64)
- else {
- /* C.ADDW (RV64/128) */
- gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s);
- }
-#endif
- break;
- case 2:
- /* C.OR -> or rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s);
- break;
- case 3:
- /* C.AND -> and rs1', rs1', rs2' */
- gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s);
- break;
- }
- break;
- }
- break;
- case 5:
- /* C.J -> jal x0, offset[11:1]*/
- gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode));
- break;
- case 6:
- /* C.BEQZ -> beq rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- case 7:
- /* C.BNEZ -> bne rs1', x0, offset[8:1]*/
- rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
- break;
- }
-}
-
-static void decode_RV32_64C2(DisasContext *ctx)
-{
- uint8_t rd, rs2;
- uint8_t funct3 = extract32(ctx->opcode, 13, 3);
-
-
- rd = GET_RD(ctx->opcode);
-
- switch (funct3) {
- case 0: /* C.SLLI -> slli rd, rd, shamt[5:0]
- C.SLLI64 -> */
- gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode));
- break;
- case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */
- gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
- break;
- case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */
- gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
- break;
- case 3:
-#if defined(TARGET_RISCV64)
- /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */
- gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
-#else
- /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */
- gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
-#endif
- break;
- case 4:
- rs2 = GET_C_RS2(ctx->opcode);
-
- if (extract32(ctx->opcode, 12, 1) == 0) {
- if (rs2 == 0) {
- /* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
- } else {
- /* C.MV -> add rd, x0, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
- }
- } else {
- if (rd == 0) {
- /* C.EBREAK -> ebreak*/
- gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
- } else {
- if (rs2 == 0) {
- /* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
- } else {
- /* C.ADD -> add rd, rd, rs2 */
- gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
- }
- }
- }
- break;
- case 5:
- /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/
- gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
- /* C.SQSP */
- break;
- case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/
- gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
- break;
- case 7:
-#if defined(TARGET_RISCV64)
- /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/
- gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode),
- GET_C_SDSP_IMM(ctx->opcode));
-#else
- /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */
- gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode),
- GET_C_SWSP_IMM(ctx->opcode));
-#endif
- break;
- }
-}
-
static void decode_RV32_64C(DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@@ -1865,140 +513,144 @@ static void decode_RV32_64C(DisasContext *ctx)
case 0:
decode_RV32_64C0(ctx);
break;
- case 1:
- decode_RV32_64C1(ctx);
- break;
- case 2:
- decode_RV32_64C2(ctx);
- break;
}
}
-static void decode_RV32_64G(DisasContext *ctx)
+#define EX_SH(amount) \
+ static int ex_shift_##amount(int imm) \
+ { \
+ return imm << amount; \
+ }
+EX_SH(1)
+EX_SH(2)
+EX_SH(3)
+EX_SH(4)
+EX_SH(12)
+
+#define REQUIRE_EXT(ctx, ext) do { \
+ if (!has_ext(ctx, ext)) { \
+ return false; \
+ } \
+} while (0)
+
+static int ex_rvc_register(int reg)
{
- int rs1;
- int rs2;
- int rd;
- uint32_t op;
- target_long imm;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rs2 = GET_RS2(ctx->opcode);
- rd = GET_RD(ctx->opcode);
- imm = GET_IMM(ctx->opcode);
-
- switch (op) {
- case OPC_RISC_LUI:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12);
- break;
- case OPC_RISC_AUIPC:
- if (rd == 0) {
- break; /* NOP */
- }
- tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) +
- ctx->base.pc_next);
- break;
- case OPC_RISC_JAL:
- imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(ctx, rd, imm);
- break;
- case OPC_RISC_JALR:
- gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_BRANCH:
- gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
- GET_B_IMM(ctx->opcode));
- break;
- case OPC_RISC_LOAD:
- gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_STORE:
- gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_ARITH_IMM:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_IMM_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
- case OPC_RISC_FP_LOAD:
- gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_FP_STORE:
- gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_ATOMIC:
- if (!has_ext(ctx, RVA)) {
- goto do_illegal;
- }
- gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
- break;
- case OPC_RISC_FMADD:
- gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FMSUB:
- gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMSUB:
- gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMADD:
- gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FP_ARITH:
- gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
- GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FENCE:
- if (ctx->opcode & 0x1000) {
- /* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- }
- break;
- case OPC_RISC_SYSTEM:
- gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
+ return 8 + reg;
}
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
+/* Include the auto-generated decoder for 32 bit insn */
+#include "decode_insn32.inc.c"
+
+static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_add_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
+static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_sub_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
+static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_mul_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+
+static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_ext32s_tl(source2, source2);
+
+ (*func)(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#endif
+
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool gen_shift(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+/* Include insn module translation function */
+#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
+#include "insn_trans/trans_rva.inc.c"
+#include "insn_trans/trans_rvf.inc.c"
+#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_privileged.inc.c"
+
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
+/* auto-generated decoder*/
+#include "decode_insn16.inc.c"
+#include "insn_trans/trans_rvc.inc.c"
+
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -2007,11 +659,16 @@ static void decode_opc(DisasContext *ctx)
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(ctx);
+ if (!decode_insn16(ctx, ctx->opcode)) {
+ /* fall back to old decoder */
+ decode_RV32_64C(ctx);
+ }
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(ctx);
+ if (!decode_insn32(ctx, ctx->opcode)) {
+ gen_exception_illegal(ctx);
+ }
}
}