target/openrisc: convert to DisasContextBase
While at it, set is_jmp to DISAS_NORETURN when generating an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1ffa4bced0
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@ -36,7 +36,8 @@
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#include "exec/log.h"
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#include "exec/log.h"
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#define LOG_DIS(str, ...) \
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#define LOG_DIS(str, ...) \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__)
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \
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## __VA_ARGS__)
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/* is_jmp field values */
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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@ -44,13 +45,10 @@
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#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
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#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
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typedef struct DisasContext {
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typedef struct DisasContext {
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TranslationBlock *tb;
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DisasContextBase base;
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target_ulong pc;
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uint32_t is_jmp;
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uint32_t mem_idx;
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uint32_t mem_idx;
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uint32_t tb_flags;
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uint32_t tb_flags;
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uint32_t delayed_branch;
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uint32_t delayed_branch;
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bool singlestep_enabled;
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} DisasContext;
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} DisasContext;
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static TCGv cpu_sr;
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static TCGv cpu_sr;
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@ -126,9 +124,9 @@ static void gen_exception(DisasContext *dc, unsigned int excp)
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static void gen_illegal_exception(DisasContext *dc)
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static void gen_illegal_exception(DisasContext *dc)
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{
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{
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_ILLEGAL);
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gen_exception(dc, EXCP_ILLEGAL);
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_NORETURN;
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}
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}
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/* not used yet, open it when we need or64. */
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/* not used yet, open it when we need or64. */
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@ -166,12 +164,12 @@ static void check_ov64s(DisasContext *dc)
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static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
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static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
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{
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{
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if (unlikely(dc->singlestep_enabled)) {
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if (unlikely(dc->base.singlestep_enabled)) {
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return false;
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return false;
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}
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}
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
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return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
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#else
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#else
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return true;
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return true;
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#endif
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#endif
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@ -182,10 +180,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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if (use_goto_tb(dc, dest)) {
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if (use_goto_tb(dc, dest)) {
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_goto_tb(n);
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tcg_gen_goto_tb(n);
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tcg_gen_exit_tb((uintptr_t)dc->tb + n);
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tcg_gen_exit_tb((uintptr_t)dc->base.tb + n);
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} else {
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_movi_tl(cpu_pc, dest);
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if (dc->singlestep_enabled) {
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if (dc->base.singlestep_enabled) {
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gen_exception(dc, EXCP_DEBUG);
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gen_exception(dc, EXCP_DEBUG);
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}
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}
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tcg_gen_exit_tb(0);
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tcg_gen_exit_tb(0);
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@ -194,16 +192,16 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
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static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
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{
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{
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target_ulong tmp_pc = dc->pc + n26 * 4;
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target_ulong tmp_pc = dc->base.pc_next + n26 * 4;
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switch (op0) {
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switch (op0) {
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case 0x00: /* l.j */
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case 0x00: /* l.j */
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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break;
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break;
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case 0x01: /* l.jal */
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case 0x01: /* l.jal */
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tcg_gen_movi_tl(cpu_R[9], dc->pc + 8);
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tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8);
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/* Optimize jal being used to load the PC for PIC. */
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/* Optimize jal being used to load the PC for PIC. */
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if (tmp_pc == dc->pc + 8) {
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if (tmp_pc == dc->base.pc_next + 8) {
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return;
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return;
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}
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}
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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@ -211,7 +209,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
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case 0x03: /* l.bnf */
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case 0x03: /* l.bnf */
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case 0x04: /* l.bf */
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case 0x04: /* l.bf */
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{
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{
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TCGv t_next = tcg_const_tl(dc->pc + 8);
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TCGv t_next = tcg_const_tl(dc->base.pc_next + 8);
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TCGv t_true = tcg_const_tl(tmp_pc);
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TCGv t_true = tcg_const_tl(tmp_pc);
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TCGv t_zero = tcg_const_tl(0);
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TCGv t_zero = tcg_const_tl(0);
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@ -227,7 +225,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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break;
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break;
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case 0x12: /* l.jalr */
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case 0x12: /* l.jalr */
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tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
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tcg_gen_movi_tl(cpu_R[9], (dc->base.pc_next + 8));
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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break;
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break;
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default:
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default:
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@ -795,7 +793,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
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return;
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return;
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}
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}
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gen_helper_rfe(cpu_env);
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gen_helper_rfe(cpu_env);
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_UPDATE;
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#endif
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#endif
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}
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}
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break;
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break;
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@ -1254,15 +1252,16 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
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switch (op0) {
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switch (op0) {
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case 0x000: /* l.sys */
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case 0x000: /* l.sys */
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LOG_DIS("l.sys %d\n", K16);
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LOG_DIS("l.sys %d\n", K16);
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_SYSCALL);
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gen_exception(dc, EXCP_SYSCALL);
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_NORETURN;
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break;
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break;
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case 0x100: /* l.trap */
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case 0x100: /* l.trap */
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LOG_DIS("l.trap %d\n", K16);
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LOG_DIS("l.trap %d\n", K16);
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_TRAP);
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gen_exception(dc, EXCP_TRAP);
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dc->base.is_jmp = DISAS_NORETURN;
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break;
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break;
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case 0x300: /* l.csync */
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case 0x300: /* l.csync */
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@ -1479,7 +1478,7 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
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{
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{
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uint32_t op0;
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uint32_t op0;
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uint32_t insn;
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uint32_t insn;
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insn = cpu_ldl_code(&cpu->env, dc->pc);
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insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
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op0 = extract32(insn, 26, 6);
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op0 = extract32(insn, 26, 6);
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switch (op0) {
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switch (op0) {
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@ -1532,14 +1531,15 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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int max_insns;
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int max_insns;
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pc_start = tb->pc;
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pc_start = tb->pc;
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dc->tb = tb;
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dc->is_jmp = DISAS_NEXT;
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dc->base.tb = tb;
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dc->pc = pc_start;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->base.pc_next = pc_start;
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dc->base.is_jmp = DISAS_NEXT;
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dc->mem_idx = cpu_mmu_index(&cpu->env, false);
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dc->mem_idx = cpu_mmu_index(&cpu->env, false);
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dc->tb_flags = tb->flags;
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dc->tb_flags = dc->base.tb->flags;
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dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
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dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
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dc->singlestep_enabled = cs->singlestep_enabled;
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next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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num_insns = 0;
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num_insns = 0;
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@ -1570,19 +1570,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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}
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}
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do {
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do {
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tcg_gen_insn_start(dc->pc, (dc->delayed_branch ? 1 : 0)
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tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
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| (num_insns ? 2 : 0));
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num_insns++;
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num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_DEBUG);
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gen_exception(dc, EXCP_DEBUG);
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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the logic setting tb->size below does the right thing. */
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dc->pc += 4;
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dc->base.pc_next += 4;
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break;
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break;
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}
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}
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@ -1590,7 +1590,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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gen_io_start();
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gen_io_start();
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}
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}
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disas_openrisc_insn(dc, cpu);
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disas_openrisc_insn(dc, cpu);
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dc->pc = dc->pc + 4;
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dc->base.pc_next += 4;
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/* delay slot */
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/* delay slot */
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if (dc->delayed_branch) {
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if (dc->delayed_branch) {
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@ -1598,15 +1598,15 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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if (!dc->delayed_branch) {
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if (!dc->delayed_branch) {
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tcg_gen_mov_tl(cpu_pc, jmp_pc);
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tcg_gen_mov_tl(cpu_pc, jmp_pc);
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tcg_gen_discard_tl(jmp_pc);
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tcg_gen_discard_tl(jmp_pc);
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_UPDATE;
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break;
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break;
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}
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}
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}
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}
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} while (!dc->is_jmp
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} while (!dc->base.is_jmp
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&& !tcg_op_buf_full()
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&& !tcg_op_buf_full()
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&& !cs->singlestep_enabled
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&& !dc->base.singlestep_enabled
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&& !singlestep
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&& !singlestep
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&& (dc->pc < next_page_start)
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&& (dc->base.pc_next < next_page_start)
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&& num_insns < max_insns);
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&& num_insns < max_insns);
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if (tb_cflags(tb) & CF_LAST_IO) {
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if (tb_cflags(tb) & CF_LAST_IO) {
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tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
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tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
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}
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}
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tcg_gen_movi_tl(cpu_ppc, dc->pc - 4);
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tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
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if (dc->is_jmp == DISAS_NEXT) {
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if (dc->base.is_jmp == DISAS_NEXT) {
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dc->is_jmp = DISAS_UPDATE;
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
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}
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}
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if (unlikely(cs->singlestep_enabled)) {
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if (unlikely(dc->base.singlestep_enabled)) {
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gen_exception(dc, EXCP_DEBUG);
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gen_exception(dc, EXCP_DEBUG);
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} else {
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} else {
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switch (dc->is_jmp) {
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switch (dc->base.is_jmp) {
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case DISAS_NEXT:
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case DISAS_NEXT:
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gen_goto_tb(dc, 0, dc->pc);
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gen_goto_tb(dc, 0, dc->base.pc_next);
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break;
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break;
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default:
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default:
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case DISAS_NORETURN:
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case DISAS_JUMP:
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case DISAS_JUMP:
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case DISAS_TB_JUMP:
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break;
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break;
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case DISAS_UPDATE:
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case DISAS_UPDATE:
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/* indicate that the hash table must be used
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/* indicate that the hash table must be used
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to find the next TB */
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to find the next TB */
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tcg_gen_exit_tb(0);
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tcg_gen_exit_tb(0);
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break;
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break;
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case DISAS_TB_JUMP:
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/* nothing more to generate */
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break;
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}
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}
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}
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}
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gen_tb_end(tb, num_insns);
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gen_tb_end(tb, num_insns);
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tb->size = dc->pc - pc_start;
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tb->size = dc->base.pc_next - pc_start;
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tb->icount = num_insns;
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tb->icount = num_insns;
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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