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target-sparc: Don't compute full flags value so often 

Avoid speculatively computing flags before every potentially trapping
operation and instead do the flags computation when a trap actually
occurs.  This gives approximately 30% speedup in emulation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2012-10-09 14:50:00 -07:00 committed by Blue Swirl
parent 6234ac09a9
commit 20132b9605
4 changed files with 26 additions and 19 deletions
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5
linux-user/main.c
View File

@ -1114,6 +1114,11 @@ void cpu_loop (CPUSPARCState *env)
while (1) {
trapnr = cpu_sparc_exec (env);
/* Compute PSR before exposing state. */
if (env->cc_op != CC_OP_FLAGS) {
cpu_get_psr(env);
}
switch (trapnr) {
#ifndef TARGET_SPARC64
case 0x88:

5
target-sparc/int32_helper.c
View File

@ -62,6 +62,11 @@ void do_interrupt(CPUSPARCState *env)
{
int cwp, intno = env->exception_index;
/* Compute PSR before exposing state. */
if (env->cc_op != CC_OP_FLAGS) {
cpu_get_psr(env);
}
#ifdef DEBUG_PCALL
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;

5
target-sparc/int64_helper.c
View File

@ -64,6 +64,11 @@ void do_interrupt(CPUSPARCState *env)
int intno = env->exception_index;
trap_state *tsptr;
/* Compute PSR before exposing state. */
if (env->cc_op != CC_OP_FLAGS) {
cpu_get_psr(env);
}
#ifdef DEBUG_PCALL
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;

30
target-sparc/translate.c
View File

@ -1005,14 +1005,17 @@ static inline void save_npc(DisasContext *dc)
}
}
static inline void save_state(DisasContext *dc)
static inline void update_psr(DisasContext *dc)
{
tcg_gen_movi_tl(cpu_pc, dc->pc);
/* flush pending conditional evaluations before exposing cpu state */
if (dc->cc_op != CC_OP_FLAGS) {
dc->cc_op = CC_OP_FLAGS;
gen_helper_compute_psr(cpu_env);
}
}
static inline void save_state(DisasContext *dc)
{
tcg_gen_movi_tl(cpu_pc, dc->pc);
save_npc(dc);
}
@ -2704,7 +2707,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
gen_helper_compute_psr(cpu_env);
update_psr(dc);
gen_helper_rdccr(cpu_dst, cpu_env);
gen_movl_TN_reg(rd, cpu_dst);
break;
@ -2783,10 +2786,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#if !defined(CONFIG_USER_ONLY)
} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
#ifndef TARGET_SPARC64
if (!supervisor(dc))
if (!supervisor(dc)) {
goto priv_insn;
gen_helper_compute_psr(cpu_env);
dc->cc_op = CC_OP_FLAGS;
}
update_psr(dc);
gen_helper_rdpsr(cpu_dst, cpu_env);
#else
CHECK_IU_FEATURE(dc, HYPV);
@ -3612,7 +3615,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
dc->cc_op = CC_OP_TSUBTV;
break;
case 0x24: /* mulscc */
gen_helper_compute_psr(cpu_env);
update_psr(dc);
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
@ -4651,12 +4654,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{
unsigned int xop = GET_FIELD(insn, 7, 12);
/* flush pending conditional evaluations before exposing
cpu state */
if (dc->cc_op != CC_OP_FLAGS) {
dc->cc_op = CC_OP_FLAGS;
gen_helper_compute_psr(cpu_env);
}
cpu_src1 = get_src1(insn, cpu_src1);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
rs2 = GET_FIELD(insn, 27, 31);
@ -5507,9 +5504,4 @@ void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos)
} else {
env->npc = npc;
}
/* flush pending conditional evaluations before exposing cpu state */
if (CC_OP != CC_OP_FLAGS) {
helper_compute_psr(env);
}
}