target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -2495,7 +2495,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
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VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
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#define VSX_MAX_MINC(name, max) \
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void helper_##name(CPUPPCState *env, uint32_t opcode, \
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void helper_##name(CPUPPCState *env, \
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ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
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{ \
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ppc_vsr_t t = *xt; \
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@ -2530,7 +2530,7 @@ VSX_MAX_MINC(xsmaxcdp, 1);
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VSX_MAX_MINC(xsmincdp, 0);
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#define VSX_MAX_MINJ(name, max) \
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void helper_##name(CPUPPCState *env, uint32_t opcode, \
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void helper_##name(CPUPPCState *env, \
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ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
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{ \
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ppc_vsr_t t = *xt; \
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@ -403,10 +403,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)
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DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)
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DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr)
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DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr)
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DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr)
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DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr)
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DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr)
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DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr)
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DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr)
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DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr)
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DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
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DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
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DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
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@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
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GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
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GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
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GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
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GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
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GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
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GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
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GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
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GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
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GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
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GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
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GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
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