s390: Disassemble some general-instruction-extension insns.
The full general-instruction-extension facility was added to binutils after the change to GPLv3. This is not the entire extension, just what we're using in TCG. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
402ce448af
commit
2024c53950
87
s390-dis.c
87
s390-dis.c
@ -172,6 +172,31 @@ static const struct s390_operand s390_operands[];
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the instruction may be optional. */
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#define S390_OPERAND_OPTIONAL 0x400
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/* QEMU-ADD */
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/* ??? Not quite the format the assembler takes, but easy to implement
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without recourse to the table generator. */
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#define S390_OPERAND_CCODE 0x800
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static const char s390_ccode_name[16][4] = {
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"n", /* 0000 */
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"o", /* 0001 */
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"h", /* 0010 */
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"nle", /* 0011 */
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"l", /* 0100 */
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"nhe", /* 0101 */
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"lh", /* 0110 */
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"ne", /* 0111 */
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"e", /* 1000 */
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"nlh", /* 1001 */
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"he", /* 1010 */
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"nl", /* 1011 */
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"le", /* 1100 */
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"nh", /* 1101 */
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"no", /* 1110 */
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"a" /* 1111 */
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};
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/* QEMU-END */
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#endif /* S390_H */
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static int init_flag = 0;
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@ -325,13 +350,16 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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continue;
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/* The instruction is valid. */
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
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else
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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/* QEMU-MOD */
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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if (s390_operands[opcode->operands[0]].flags & S390_OPERAND_CCODE)
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separator = 0;
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else
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separator = '\t';
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/* QEMU-END */
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/* Extract the operands. */
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separator = 0;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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unsigned int value;
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@ -363,6 +391,15 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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(*info->print_address_func) (memaddr + (int) value, info);
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else if (operand->flags & S390_OPERAND_SIGNED)
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(*info->fprintf_func) (info->stream, "%i", (int) value);
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/* QEMU-ADD */
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else if (operand->flags & S390_OPERAND_CCODE)
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{
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(*info->fprintf_func) (info->stream, "%s",
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s390_ccode_name[(int) value]);
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separator = '\t';
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continue;
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}
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/* QEMU-END */
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else
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(*info->fprintf_func) (info->stream, "%u", value);
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@ -543,8 +580,16 @@ static const struct s390_operand s390_operands[] =
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#define M_16 42 /* 4 bit optional mask starting at 16 */
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{ 4, 16, S390_OPERAND_OPTIONAL },
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#define RO_28 43 /* optional GPR starting at position 28 */
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{ 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }
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{ 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
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/* QEMU-ADD: */
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#define M4_12 44 /* 4-bit condition-code starting at 12 */
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{ 4, 12, S390_OPERAND_CCODE },
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#define M4_32 45 /* 4-bit condition-code starting at 32 */
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{ 4, 32, S390_OPERAND_CCODE },
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#define I8_32 46 /* 8 bit signed value starting at 32 */
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{ 8, 32, S390_OPERAND_SIGNED },
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/* QEMU-END */
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};
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@ -755,6 +800,14 @@ static const struct s390_operand s390_operands[] =
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#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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/* QEMU-ADD: */
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#define INSTR_RIE_MRRP 6, { M4_32,R_8,R_12,J16_16,0,0 } /* e.g. crj */
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#define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
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#define INSTR_RIE_MRIP 6, { M4_12,R_8,I8_32,J16_16,0,0 } /* e.g. cij */
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#define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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/* QEMU-END */
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/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
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static const struct s390_opcode s390_opformats[] =
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@ -1092,6 +1145,10 @@ static const struct s390_opcode s390_opcodes[] =
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{ "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
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{ "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
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{ "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
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/* QEMU-ADD: */
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{ "msfi", OP16(0xc201ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
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{ "msgfi", OP16(0xc200ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
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/* QEMU-END */
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{ "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
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{ "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
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{ "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
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@ -1716,7 +1773,23 @@ static const struct s390_opcode s390_opcodes[] =
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{ "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5},
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{ "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
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{ "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
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{ "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0}
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{ "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
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/* QEMU-ADD: */
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{ "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
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{ "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
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{ "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
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{ "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
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{ "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
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{ "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
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{ "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
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{ "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
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{ "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
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{ "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
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{ "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
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/* QEMU-END */
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};
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static const int s390_num_opcodes =
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