target-xtensa: tests: pre-process tests linker script

Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
core configuration. Instead of hard-coding dc232 defaults pull endianness,
number of high-priority interrupts and location of vectors from the core
configuration and pass it through the C preprocessor.

While at it clean up tabs and align the initial stack on 16 bytes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2014-09-17 21:13:09 -07:00
parent dec71d2d63
commit 20303e42d4
3 changed files with 137 additions and 115 deletions

View File

@ -13,6 +13,7 @@ SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
SIMDEBUG = --gdbserve=0
endif
HOST_CC = gcc
CC = $(CROSS)gcc
AS = $(CROSS)gcc -x assembler-with-cpp
LD = $(CROSS)ld
@ -21,7 +22,7 @@ XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld
LDFLAGS = -Tlinker.ld
CRT = crt.o vectors.o
@ -59,13 +60,16 @@ TESTCASES += test_windowed.tst
all: build
linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
$(HOST_CC) $(XTENSA_INC) -E -P $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.c
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.S
$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
%.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
build: $(TESTCASES)
@ -85,4 +89,4 @@ host-debug-%.tst: %.tst
gdb --args $(SIM) $(SIMFLAGS) ./$<
clean:
$(RM) -fr $(TESTCASES) $(CRT)
$(RM) -fr $(TESTCASES) $(CRT) linker.ld

View File

@ -1,112 +0,0 @@
OUTPUT_FORMAT("elf32-xtensa-le")
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = 0xd0000000, LENGTH = 0x08000000 /* 128M */
rom : ORIGIN = 0xfe000000, LENGTH = 0x00001000 /* 4k */
}
SECTIONS
{
.init :
{
*(.init)
*(.init.*)
} > rom
.vector :
{
. = 0x00000000;
*(.vector.window_overflow_4)
*(.vector.window_overflow_4.*)
. = 0x00000040;
*(.vector.window_underflow_4)
*(.vector.window_underflow_4.*)
. = 0x00000080;
*(.vector.window_overflow_8)
*(.vector.window_overflow_8.*)
. = 0x000000c0;
*(.vector.window_underflow_8)
*(.vector.window_underflow_8.*)
. = 0x00000100;
*(.vector.window_overflow_12)
*(.vector.window_overflow_12.*)
. = 0x00000140;
*(.vector.window_underflow_12)
*(.vector.window_underflow_12.*)
. = 0x00000180;
*(.vector.level2)
*(.vector.level2.*)
. = 0x000001c0;
*(.vector.level3)
*(.vector.level3.*)
. = 0x00000200;
*(.vector.level4)
*(.vector.level4.*)
. = 0x00000240;
*(.vector.level5)
*(.vector.level5.*)
. = 0x00000280;
*(.vector.level6)
*(.vector.level6.*)
. = 0x000002c0;
*(.vector.level7)
*(.vector.level7.*)
. = 0x00000300;
*(.vector.kernel)
*(.vector.kernel.*)
. = 0x00000340;
*(.vector.user)
*(.vector.user.*)
. = 0x000003c0;
*(.vector.double)
*(.vector.double.*)
} > ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

View File

@ -0,0 +1,130 @@
#include <core-isa.h>
#if XTENSA_HAVE_BE
OUTPUT_FORMAT("elf32-xtensa-be")
#else
OUTPUT_FORMAT("elf32-xtensa-le")
#endif
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
}
SECTIONS
{
.init :
{
*(.init)
*(.init.*)
} > rom
.vector :
{
. = XCHAL_WINDOW_OF4_VECOFS;
*(.vector.window_overflow_4)
*(.vector.window_overflow_4.*)
. = XCHAL_WINDOW_UF4_VECOFS;
*(.vector.window_underflow_4)
*(.vector.window_underflow_4.*)
. = XCHAL_WINDOW_OF8_VECOFS;
*(.vector.window_overflow_8)
*(.vector.window_overflow_8.*)
. = XCHAL_WINDOW_UF8_VECOFS;
*(.vector.window_underflow_8)
*(.vector.window_underflow_8.*)
. = XCHAL_WINDOW_OF12_VECOFS;
*(.vector.window_overflow_12)
*(.vector.window_overflow_12.*)
. = XCHAL_WINDOW_UF12_VECOFS;
*(.vector.window_underflow_12)
*(.vector.window_underflow_12.*)
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
. = XCHAL_INTLEVEL2_VECOFS;
*(.vector.level2)
*(.vector.level2.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
. = XCHAL_INTLEVEL3_VECOFS;
*(.vector.level3)
*(.vector.level3.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
. = XCHAL_INTLEVEL4_VECOFS;
*(.vector.level4)
*(.vector.level4.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
. = XCHAL_INTLEVEL5_VECOFS;
*(.vector.level5)
*(.vector.level5.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
. = XCHAL_INTLEVEL6_VECOFS;
*(.vector.level6)
*(.vector.level6.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
. = XCHAL_INTLEVEL7_VECOFS;
*(.vector.level7)
*(.vector.level7.*)
#endif
. = XCHAL_KERNEL_VECOFS;
*(.vector.kernel)
*(.vector.kernel.*)
. = XCHAL_USER_VECOFS;
*(.vector.user)
*(.vector.user.*)
. = XCHAL_DOUBLEEXC_VECOFS;
*(.vector.double)
*(.vector.double.*)
} > ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);