target/hexagon: fix some occurrences of -Wshadow=local
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()` are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231008220945.983643-3-bcain@quicinc.com>
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@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
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tmp128 = fSHIFTR128(tmp128, SHIFT);\
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DST = fCAST16S_8S(tmp128);\
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} else {\
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size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
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size16s_t src_128 = fCAST8S_16S(SRC); \
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size16s_t tmp128 = fADD128(src_128, rndbit_128);\
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rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
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src_128 = fCAST8S_16S(SRC); \
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tmp128 = fADD128(src_128, rndbit_128);\
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tmp128 = fSHIFTR128(tmp128, SHIFT);\
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DST = fCAST16S_8S(tmp128);\
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}
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@ -201,7 +201,7 @@
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} while (0)
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#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
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do { \
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uintptr_t ra = GETPC(); \
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ra = GETPC(); \
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for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
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if (test_bit(i, env->vtcm_log.mask)) { \
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TYPE dst = 0; \
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@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
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void HELPER(commit_hvx_stores)(CPUHexagonState *env)
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{
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uintptr_t ra = GETPC();
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int i;
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/* Normal (possibly masked) vector store */
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for (i = 0; i < VSTORES_MAX; i++) {
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for (int i = 0; i < VSTORES_MAX; i++) {
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if (env->vstore_pending[i]) {
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env->vstore_pending[i] = 0;
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target_ulong va = env->vstore[i].va;
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@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
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g_assert_not_reached();
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}
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} else {
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for (i = 0; i < sizeof(MMVector); i++) {
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for (int i = 0; i < sizeof(MMVector); i++) {
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if (test_bit(i, env->vtcm_log.mask)) {
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cpu_stb_data_ra(env, env->vtcm_log.va[i],
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env->vtcm_log.data.ub[i], ra);
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@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
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static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
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uintptr_t retaddr)
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{
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int i;
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/* Normal (possibly masked) vector store */
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for (i = 0; i < VSTORES_MAX; i++) {
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for (int i = 0; i < VSTORES_MAX; i++) {
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if (env->vstore_pending[i]) {
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target_ulong va = env->vstore[i].va;
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int size = env->vstore[i].size;
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@ -553,7 +553,7 @@ static void gen_start_packet(DisasContext *ctx)
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/* Preload the predicated registers into get_result_gpr(ctx, i) */
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if (ctx->need_commit &&
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!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
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int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
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i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
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while (i < TOTAL_PER_THREAD_REGS) {
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tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]);
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i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
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@ -566,7 +566,7 @@ static void gen_start_packet(DisasContext *ctx)
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* Only endloop instructions conditionally write to pred registers
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*/
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if (ctx->need_commit && pkt->pkt_has_endloop) {
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for (int i = 0; i < ctx->preg_log_idx; i++) {
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for (i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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ctx->new_pred_value[pred_num] = tcg_temp_new();
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tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_num]);
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@ -575,7 +575,7 @@ static void gen_start_packet(DisasContext *ctx)
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/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
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if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
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int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
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i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
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while (i < NUM_VREGS) {
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const intptr_t VdV_off =
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ctx_future_vreg_off(ctx, i, 1, true);
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@ -588,7 +588,7 @@ static void gen_start_packet(DisasContext *ctx)
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}
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}
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if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
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int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
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i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
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while (i < NUM_VREGS) {
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const intptr_t VdV_off =
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ctx_tmp_vreg_off(ctx, i, 1, true);
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@ -1228,7 +1228,7 @@ void hexagon_translate_init(void)
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offsetof(CPUHexagonState, mem_log_stores[i].data64),
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store_val64_names[i]);
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}
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for (int i = 0; i < VSTORES_MAX; i++) {
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for (i = 0; i < VSTORES_MAX; i++) {
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snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
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hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
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offsetof(CPUHexagonState, vstore[i].va),
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