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target/arm/kvm: Move kvm_arm_verify_ext_dabt_pending and unexport

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-12-19 17:57:39 +00:00 committed by Peter Maydell
parent dd2157d291
commit 20c83dc9ed
3 changed files with 57 additions and 59 deletions
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57
target/arm/kvm.c
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@ -793,6 +793,63 @@ int kvm_get_vcpu_events(ARMCPU *cpu)
return 0;
}
#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
/*
* ESR_EL1
* ISS encoding
* AARCH64: DFSC, bits [5:0]
* AARCH32:
* TTBCR.EAE == 0
* FS[4] - DFSR[10]
* FS[3:0] - DFSR[3:0]
* TTBCR.EAE == 1
* FS, bits [5:0]
*/
#define ESR_DFSC(aarch64, lpae, v) \
((aarch64 || (lpae)) ? ((v) & 0x3F) \
: (((v) >> 6) | ((v) & 0x1F)))
#define ESR_DFSC_EXTABT(aarch64, lpae) \
((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
/**
* kvm_arm_verify_ext_dabt_pending:
* @cs: CPUState
*
* Verify the fault status code wrt the Ext DABT injection
*
* Returns: true if the fault status code is as expected, false otherwise
*/
static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
{
uint64_t dfsr_val;
if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
int lpae = 0;
if (!aarch64_mode) {
uint64_t ttbcr;
if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
lpae = arm_feature(env, ARM_FEATURE_LPAE)
&& (ttbcr & TTBCR_EAE);
}
}
/*
* The verification here is based on the DFSC bits
* of the ESR_EL1 reg only
*/
return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
ESR_DFSC_EXTABT(aarch64_mode, lpae));
}
return false;
}
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
{
ARMCPU *cpu = ARM_CPU(cs);

49
target/arm/kvm64.c
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@ -1213,52 +1213,3 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
return false;
}
#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
/*
* ESR_EL1
* ISS encoding
* AARCH64: DFSC, bits [5:0]
* AARCH32:
* TTBCR.EAE == 0
* FS[4] - DFSR[10]
* FS[3:0] - DFSR[3:0]
* TTBCR.EAE == 1
* FS, bits [5:0]
*/
#define ESR_DFSC(aarch64, lpae, v) \
((aarch64 || (lpae)) ? ((v) & 0x3F) \
: (((v) >> 6) | ((v) & 0x1F)))
#define ESR_DFSC_EXTABT(aarch64, lpae) \
((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
{
uint64_t dfsr_val;
if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
int lpae = 0;
if (!aarch64_mode) {
uint64_t ttbcr;
if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
lpae = arm_feature(env, ARM_FEATURE_LPAE)
&& (ttbcr & TTBCR_EAE);
}
}
/*
* The verification here is based on the DFSC bits
* of the ESR_EL1 reg only
*/
return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
ESR_DFSC_EXTABT(aarch64_mode, lpae));
}
return false;
}

10
target/arm/kvm_arm.h
View File

@ -472,14 +472,4 @@ bool kvm_arm_hw_debug_active(CPUState *cs);
struct kvm_guest_debug_arch;
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
/**
* kvm_arm_verify_ext_dabt_pending:
* @cs: CPUState
*
* Verify the fault status code wrt the Ext DABT injection
*
* Returns: true if the fault status code is as expected, false otherwise
*/
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
#endif