ppc/pnv: turn PnvPHB4 into a PnvPHB backend
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the PCI bus is going to be initialized by the PnvPHB parent. Functions that needs to access the bus via a PnvPHB4 object can do so via the phb4->phb_base pointer. pnv_phb4_pec now creates a PnvPHB object. The powernv9 machine class will create PnvPHB devices with version '4'. powernv10 will create using version '5'. Both are using global machine properties in their class_init() to do that. These changes will benefit us when adding PnvPHB user creatable devices for powernv9 and powernv10. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-6-danielhb413@gmail.com>
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@ -33,7 +33,7 @@
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static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
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static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
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{
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(phb);
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PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
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uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
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uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
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uint8_t bus, devfn;
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uint8_t bus, devfn;
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@ -129,7 +129,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off,
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static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
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static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
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unsigned size, uint64_t val)
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unsigned size, uint64_t val)
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{
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(phb);
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PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
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PCIDevice *pdev;
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PCIDevice *pdev;
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if (size != 4) {
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if (size != 4) {
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@ -150,7 +150,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
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static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
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static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
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unsigned size)
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unsigned size)
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{
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(phb);
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PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
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PCIDevice *pdev;
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PCIDevice *pdev;
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uint64_t val;
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uint64_t val;
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@ -1558,8 +1558,6 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
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static void pnv_phb4_realize(DeviceState *dev, Error **errp)
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static void pnv_phb4_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvPHB4 *phb = PNV_PHB4(dev);
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PnvPHB4 *phb = PNV_PHB4(dev);
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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XiveSource *xsrc = &phb->xsrc;
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XiveSource *xsrc = &phb->xsrc;
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int nr_irqs;
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int nr_irqs;
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char name[32];
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char name[32];
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@ -1573,12 +1571,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
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memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
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memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
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name, 0x2000);
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name, 0x2000);
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pnv_phb4_bus_init(dev, phb);
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/* Add a single Root port if running with defaults */
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pnv_phb_attach_root_port(pci, pecc->rp_model,
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phb->phb_id, phb->chip_id);
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/* Setup XIVE Source */
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/* Setup XIVE Source */
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if (phb->big_phb) {
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if (phb->big_phb) {
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nr_irqs = PNV_PHB4_MAX_INTs;
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nr_irqs = PNV_PHB4_MAX_INTs;
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@ -1598,16 +1590,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
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pnv_phb4_xscom_realize(phb);
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pnv_phb4_xscom_realize(phb);
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}
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}
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static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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PnvPHB4 *phb = PNV_PHB4(host_bridge);
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snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
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phb->chip_id, phb->phb_id);
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return phb->bus_path;
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}
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/*
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/*
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* Address base trigger mode (POWER10)
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* Address base trigger mode (POWER10)
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*
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*
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@ -1692,19 +1674,17 @@ static Property pnv_phb4_properties[] = {
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DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
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DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
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DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
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DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
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PnvPhb4PecState *),
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PnvPhb4PecState *),
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DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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static void pnv_phb4_class_init(ObjectClass *klass, void *data)
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static void pnv_phb4_class_init(ObjectClass *klass, void *data)
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{
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{
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
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XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
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hc->root_bus_path = pnv_phb4_root_bus_path;
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dc->realize = pnv_phb4_realize;
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dc->realize = pnv_phb4_realize;
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device_class_set_props(dc, pnv_phb4_properties);
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device_class_set_props(dc, pnv_phb4_properties);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->user_creatable = false;
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dc->user_creatable = false;
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xfc->notify = pnv_phb4_xive_notify;
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xfc->notify = pnv_phb4_xive_notify;
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@ -1712,7 +1692,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data)
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static const TypeInfo pnv_phb4_type_info = {
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static const TypeInfo pnv_phb4_type_info = {
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.name = TYPE_PNV_PHB4,
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.name = TYPE_PNV_PHB4,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.parent = TYPE_DEVICE,
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.instance_init = pnv_phb4_instance_init,
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.instance_init = pnv_phb4_instance_init,
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.instance_size = sizeof(PnvPHB4),
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.instance_size = sizeof(PnvPHB4),
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.class_init = pnv_phb4_class_init,
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.class_init = pnv_phb4_class_init,
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@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
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int stack_no,
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int stack_no,
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Error **errp)
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Error **errp)
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{
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{
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
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PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
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PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type));
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int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
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int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
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object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
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object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
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20
hw/ppc/pnv.c
20
hw/ppc/pnv.c
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@ -672,11 +672,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
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static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
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static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
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{
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{
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Monitor *mon = opaque;
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Monitor *mon = opaque;
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PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
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PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
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if (phb4) {
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if (!phb) {
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pnv_phb4_pic_print_info(phb4, mon);
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return 0;
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}
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}
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pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
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return 0;
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return 0;
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}
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}
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@ -2147,8 +2150,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
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PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
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PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
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static const char compat[] = "qemu,powernv9\0ibm,powernv";
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static const char compat[] = "qemu,powernv9\0ibm,powernv";
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static GlobalProperty phb_compat[] = {
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{ TYPE_PNV_PHB, "version", "4" },
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};
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mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
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mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
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compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
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xfc->match_nvt = pnv_match_nvt;
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xfc->match_nvt = pnv_match_nvt;
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mc->alias = "powernv";
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mc->alias = "powernv";
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@ -2165,8 +2174,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
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XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
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XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
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static const char compat[] = "qemu,powernv10\0ibm,powernv";
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static const char compat[] = "qemu,powernv10\0ibm,powernv";
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static GlobalProperty phb_compat[] = {
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{ TYPE_PNV_PHB, "version", "5" },
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};
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mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
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mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
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compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
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pmc->compat = compat;
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pmc->compat = compat;
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pmc->compat_size = sizeof(compat);
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pmc->compat_size = sizeof(compat);
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@ -18,6 +18,7 @@
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typedef struct PnvPhb4PecState PnvPhb4PecState;
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typedef struct PnvPhb4PecState PnvPhb4PecState;
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typedef struct PnvPhb4PecStack PnvPhb4PecStack;
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typedef struct PnvPhb4PecStack PnvPhb4PecStack;
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typedef struct PnvPHB4 PnvPHB4;
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typedef struct PnvPHB4 PnvPHB4;
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typedef struct PnvPHB PnvPHB;
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typedef struct PnvChip PnvChip;
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typedef struct PnvChip PnvChip;
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/*
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/*
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@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
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#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
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#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
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struct PnvPHB4 {
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struct PnvPHB4 {
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PCIExpressHost parent_obj;
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DeviceState parent;
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PnvPHB *phb_base;
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uint32_t chip_id;
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uint32_t chip_id;
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uint32_t phb_id;
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uint32_t phb_id;
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