hw/misc/tz-msc: Model TrustZone Master Security Controller
Implement a model of the TrustZone Master Securtiy Controller, as documented in the Arm CoreLink SIE-200 System IP for Embedded TRM (DDI0571G): https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g The MSC is intended to sit in front of a device which can be a bus master (eg a DMA controller) and programmably gate its transactions. This allows a bus-mastering device to be controlled by non-secure code but still restricted from making accesses to addresses which are secure-only. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
06e65af39b
commit
211e701d66
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@ -465,6 +465,8 @@ F: hw/misc/tz-ppc.c
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F: include/hw/misc/tz-ppc.h
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F: hw/misc/tz-mpc.c
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F: include/hw/misc/tz-mpc.h
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F: hw/misc/tz-msc.c
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F: include/hw/misc/tz-msc.h
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ARM cores
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M: Peter Maydell <peter.maydell@linaro.org>
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@ -111,6 +111,7 @@ CONFIG_MPS2_FPGAIO=y
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CONFIG_MPS2_SCC=y
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CONFIG_TZ_MPC=y
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CONFIG_TZ_MSC=y
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CONFIG_TZ_PPC=y
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CONFIG_IOTKIT=y
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CONFIG_IOTKIT_SECCTL=y
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@ -64,6 +64,7 @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
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obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
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obj-$(CONFIG_TZ_MPC) += tz-mpc.o
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obj-$(CONFIG_TZ_MSC) += tz-msc.o
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obj-$(CONFIG_TZ_PPC) += tz-ppc.o
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obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
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obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
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@ -92,6 +92,15 @@ tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secur
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tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s"
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tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64
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# hw/misc/tz-msc.c
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tz_msc_reset(void) "TZ MSC: reset"
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tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d"
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tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d"
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tz_msc_irq_enable(int level) "TZ MSC: int_enable = %d"
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tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d"
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tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d"
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tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked"
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# hw/misc/tz-ppc.c
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tz_ppc_reset(void) "TZ PPC: reset"
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tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d"
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@ -0,0 +1,308 @@
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/*
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* ARM TrustZone master security controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/tz-msc.h"
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static void tz_msc_update_irq(TZMSC *s)
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{
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bool level = s->irq_status;
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trace_tz_msc_update_irq(level);
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qemu_set_irq(s->irq, level);
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}
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static void tz_msc_cfg_nonsec(void *opaque, int n, int level)
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{
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TZMSC *s = TZ_MSC(opaque);
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trace_tz_msc_cfg_nonsec(level);
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s->cfg_nonsec = level;
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}
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static void tz_msc_cfg_sec_resp(void *opaque, int n, int level)
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{
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TZMSC *s = TZ_MSC(opaque);
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trace_tz_msc_cfg_sec_resp(level);
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s->cfg_sec_resp = level;
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}
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static void tz_msc_irq_clear(void *opaque, int n, int level)
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{
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TZMSC *s = TZ_MSC(opaque);
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trace_tz_msc_irq_clear(level);
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s->irq_clear = level;
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if (level) {
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s->irq_status = false;
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tz_msc_update_irq(s);
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}
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}
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/* The MSC may either block a transaction by aborting it, block a
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* transaction by making it RAZ/WI, allow it through with
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* MemTxAttrs indicating a secure transaction, or allow it with
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* MemTxAttrs indicating a non-secure transaction.
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*/
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typedef enum MSCAction {
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MSCBlockAbort,
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MSCBlockRAZWI,
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MSCAllowSecure,
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MSCAllowNonSecure,
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} MSCAction;
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static MSCAction tz_msc_check(TZMSC *s, hwaddr addr)
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{
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/*
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* Check whether to allow an access from the bus master, returning
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* an MSCAction indicating the required behaviour. If the transaction
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* is blocked, the caller must check cfg_sec_resp to determine
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* whether to abort or RAZ/WI the transaction.
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*/
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IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(s->idau);
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IDAUInterface *ii = IDAU_INTERFACE(s->idau);
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bool idau_exempt = false, idau_ns = true, idau_nsc = true;
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int idau_region = IREGION_NOTVALID;
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iic->check(ii, addr, &idau_region, &idau_exempt, &idau_ns, &idau_nsc);
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if (idau_exempt) {
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/*
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* Uncheck region -- OK, transaction type depends on
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* whether bus master is configured as Secure or NonSecure
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*/
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return s->cfg_nonsec ? MSCAllowNonSecure : MSCAllowSecure;
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}
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if (idau_ns) {
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/* NonSecure region -- always forward as NS transaction */
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return MSCAllowNonSecure;
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}
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if (!s->cfg_nonsec) {
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/* Access to Secure region by Secure bus master: OK */
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return MSCAllowSecure;
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}
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/* Attempted access to Secure region by NS bus master: block */
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trace_tz_msc_access_blocked(addr);
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if (!s->cfg_sec_resp) {
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return MSCBlockRAZWI;
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}
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/*
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* The TRM isn't clear on behaviour if irq_clear is high when a
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* transaction is blocked. We assume that the MSC behaves like the
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* PPC, where holding irq_clear high suppresses the interrupt.
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*/
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if (!s->irq_clear) {
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s->irq_status = true;
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tz_msc_update_irq(s);
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}
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return MSCBlockAbort;
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}
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static MemTxResult tz_msc_read(void *opaque, hwaddr addr, uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZMSC *s = opaque;
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AddressSpace *as = &s->downstream_as;
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uint64_t data;
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MemTxResult res;
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switch (tz_msc_check(s, addr)) {
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case MSCBlockAbort:
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return MEMTX_ERROR;
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case MSCBlockRAZWI:
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*pdata = 0;
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return MEMTX_OK;
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case MSCAllowSecure:
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attrs.secure = 1;
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attrs.unspecified = 0;
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break;
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case MSCAllowNonSecure:
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attrs.secure = 0;
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attrs.unspecified = 0;
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break;
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}
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switch (size) {
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case 1:
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data = address_space_ldub(as, addr, attrs, &res);
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break;
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case 2:
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data = address_space_lduw_le(as, addr, attrs, &res);
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break;
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case 4:
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data = address_space_ldl_le(as, addr, attrs, &res);
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break;
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case 8:
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data = address_space_ldq_le(as, addr, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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*pdata = data;
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return res;
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}
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static MemTxResult tz_msc_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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{
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TZMSC *s = opaque;
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AddressSpace *as = &s->downstream_as;
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MemTxResult res;
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switch (tz_msc_check(s, addr)) {
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case MSCBlockAbort:
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return MEMTX_ERROR;
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case MSCBlockRAZWI:
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return MEMTX_OK;
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case MSCAllowSecure:
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attrs.secure = 1;
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attrs.unspecified = 0;
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break;
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case MSCAllowNonSecure:
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attrs.secure = 0;
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attrs.unspecified = 0;
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break;
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}
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switch (size) {
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case 1:
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address_space_stb(as, addr, val, attrs, &res);
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break;
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case 2:
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address_space_stw_le(as, addr, val, attrs, &res);
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break;
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case 4:
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address_space_stl_le(as, addr, val, attrs, &res);
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break;
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case 8:
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address_space_stq_le(as, addr, val, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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return res;
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}
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static const MemoryRegionOps tz_msc_ops = {
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.read_with_attrs = tz_msc_read,
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.write_with_attrs = tz_msc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void tz_msc_reset(DeviceState *dev)
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{
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TZMSC *s = TZ_MSC(dev);
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trace_tz_msc_reset();
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s->cfg_sec_resp = false;
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s->cfg_nonsec = false;
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s->irq_clear = 0;
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s->irq_status = 0;
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}
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static void tz_msc_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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TZMSC *s = TZ_MSC(obj);
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qdev_init_gpio_in_named(dev, tz_msc_cfg_nonsec, "cfg_nonsec", 1);
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qdev_init_gpio_in_named(dev, tz_msc_cfg_sec_resp, "cfg_sec_resp", 1);
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qdev_init_gpio_in_named(dev, tz_msc_irq_clear, "irq_clear", 1);
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qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
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}
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static void tz_msc_realize(DeviceState *dev, Error **errp)
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{
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Object *obj = OBJECT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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TZMSC *s = TZ_MSC(dev);
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const char *name = "tz-msc-downstream";
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uint64_t size;
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/*
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* We can't create the upstream end of the port until realize,
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* as we don't know the size of the MR used as the downstream until then.
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* We insist on having a downstream, to avoid complicating the
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* code with handling the "don't know how big this is" case. It's easy
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* enough for the user to create an unimplemented_device as downstream
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* if they have nothing else to plug into this.
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*/
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if (!s->downstream) {
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error_setg(errp, "MSC 'downstream' link not set");
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return;
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}
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if (!s->idau) {
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error_setg(errp, "MSC 'idau' link not set");
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return;
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}
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size = memory_region_size(s->downstream);
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address_space_init(&s->downstream_as, s->downstream, name);
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memory_region_init_io(&s->upstream, obj, &tz_msc_ops, s, name, size);
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sysbus_init_mmio(sbd, &s->upstream);
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}
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static const VMStateDescription tz_msc_vmstate = {
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.name = "tz-msc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(cfg_nonsec, TZMSC),
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VMSTATE_BOOL(cfg_sec_resp, TZMSC),
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VMSTATE_BOOL(irq_clear, TZMSC),
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VMSTATE_BOOL(irq_status, TZMSC),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property tz_msc_properties[] = {
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DEFINE_PROP_LINK("downstream", TZMSC, downstream,
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TYPE_MEMORY_REGION, MemoryRegion *),
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DEFINE_PROP_LINK("idau", TZMSC, idau,
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TYPE_IDAU_INTERFACE, IDAUInterface *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void tz_msc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = tz_msc_realize;
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dc->vmsd = &tz_msc_vmstate;
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dc->reset = tz_msc_reset;
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dc->props = tz_msc_properties;
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}
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static const TypeInfo tz_msc_info = {
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.name = TYPE_TZ_MSC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(TZMSC),
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.instance_init = tz_msc_init,
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.class_init = tz_msc_class_init,
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};
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static void tz_msc_register_types(void)
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{
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type_register_static(&tz_msc_info);
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}
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type_init(tz_msc_register_types);
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@ -0,0 +1,79 @@
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/*
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* ARM TrustZone master security controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the TrustZone master security controller (MSC).
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* It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
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* (DDI 0571G):
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* https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
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*
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* The MSC sits in front of a device which can be a bus master (such as
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* a DMA controller) and allows secure software to configure it to either
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* pass through or reject transactions made by that bus master.
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* Rejected transactions may be configured to either be aborted, or to
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* behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
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*
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* The MSC has no register interface -- it is configured purely by a
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* collection of input signals from other hardware in the system. Typically
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* they are either hardwired or exposed in an ad-hoc register interface by
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* the SoC that uses the MSC.
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*
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* We don't currently implement the irq_enable GPIO input, because on
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* the MPS2 FPGA images it is always tied high, which is awkward to
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* implement in QEMU.
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*
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* QEMU interface:
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* + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be
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* treated as nonsecure, or 0 for secure
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* + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
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* result in a transaction error, or 0 for the transaction to RAZ/WI
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* + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
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* + Named GPIO output "irq": set for a transaction-failed interrupt
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* + Property "downstream": MemoryRegion defining where bus master transactions
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* are made if they are not blocked
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* + Property "idau": an object implementing IDAUInterface, which defines which
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* addresses should be treated as secure and which as non-secure.
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* This need not be the same IDAU as the one used by the CPU.
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* + sysbus MMIO region 0: MemoryRegion defining the upstream end of the MSC;
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* this should be passed to the bus master device as the region it should
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* make memory transactions to
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*/
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#ifndef TZ_MSC_H
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#define TZ_MSC_H
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#include "hw/sysbus.h"
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#include "target/arm/idau.h"
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#define TYPE_TZ_MSC "tz-msc"
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#define TZ_MSC(obj) OBJECT_CHECK(TZMSC, (obj), TYPE_TZ_MSC)
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typedef struct TZMSC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/* State: these just track the values of our input signals */
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bool cfg_nonsec;
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bool cfg_sec_resp;
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bool irq_clear;
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/* State: are we asserting irq ? */
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bool irq_status;
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qemu_irq irq;
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MemoryRegion *downstream;
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AddressSpace downstream_as;
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MemoryRegion upstream;
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IDAUInterface *idau;
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} TZMSC;
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#endif
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