tcg/arm: Implement tcg_out_dup*_vec
Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
parent
2df2a8cf77
commit
213e8d8473
@ -175,8 +175,13 @@ typedef enum {
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INSN_VORR = 0xf2200110,
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INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
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INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */
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INSN_VLDR_D = 0xed100b00, /* VLDR.64 */
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INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
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INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */
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INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
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INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */
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} ARMInsn;
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#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
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@ -195,6 +200,14 @@ static const uint8_t tcg_cond_to_arm_cond[] = {
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[TCG_COND_GTU] = COND_HI,
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};
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static int encode_imm(uint32_t imm);
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/* TCG private relocation type: add with pc+imm8 */
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#define R_ARM_PC8 11
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/* TCG private relocation type: vldr with imm8 << 2 */
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#define R_ARM_PC11 12
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static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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{
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const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
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@ -226,16 +239,52 @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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return false;
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}
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static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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{
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const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
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ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
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if (offset >= -0xff && offset <= 0xff) {
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tcg_insn_unit insn = *src_rw;
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bool u = (offset >= 0);
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if (!u) {
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offset = -offset;
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}
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insn = deposit32(insn, 23, 1, u);
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insn = deposit32(insn, 0, 8, offset);
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*src_rw = insn;
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return true;
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}
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return false;
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}
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static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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{
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const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
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ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
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int rot = encode_imm(offset);
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if (rot >= 0) {
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*src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
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return true;
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}
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return false;
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}
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static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend)
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{
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tcg_debug_assert(addend == 0);
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if (type == R_ARM_PC24) {
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switch (type) {
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case R_ARM_PC24:
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return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
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} else if (type == R_ARM_PC13) {
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case R_ARM_PC13:
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return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
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} else {
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case R_ARM_PC11:
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return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
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case R_ARM_PC8:
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return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
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default:
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g_assert_not_reached();
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}
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}
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@ -275,7 +324,7 @@ static inline uint32_t rotl(uint32_t val, int n)
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/* ARM immediates for ALU instructions are made of an unsigned 8-bit
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right-rotated by an even amount between 0 and 30. */
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static inline int encode_imm(uint32_t imm)
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static int encode_imm(uint32_t imm)
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{
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int shift;
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@ -302,6 +351,79 @@ static inline int check_fit_imm(uint32_t imm)
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return encode_imm(imm) >= 0;
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}
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/* Return true if v16 is a valid 16-bit shifted immediate. */
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static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
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{
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if (v16 == (v16 & 0xff)) {
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*cmode = 0x8;
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*imm8 = v16 & 0xff;
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return true;
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} else if (v16 == (v16 & 0xff00)) {
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*cmode = 0xa;
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*imm8 = v16 >> 8;
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return true;
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}
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return false;
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}
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/* Return true if v32 is a valid 32-bit shifted immediate. */
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static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
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{
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if (v32 == (v32 & 0xff)) {
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*cmode = 0x0;
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*imm8 = v32 & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff00)) {
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*cmode = 0x2;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff0000)) {
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*cmode = 0x4;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff000000)) {
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*cmode = 0x6;
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*imm8 = v32 >> 24;
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return true;
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}
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return false;
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}
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/* Return true if v32 is a valid 32-bit shifting ones immediate. */
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static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
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{
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if ((v32 & 0xffff00ff) == 0xff) {
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*cmode = 0xc;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if ((v32 & 0xff00ffff) == 0xffff) {
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*cmode = 0xd;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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}
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return false;
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}
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/*
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* Return non-zero if v32 can be formed by MOVI+ORR.
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* Place the parameters for MOVI in (cmode, imm8).
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* Return the cmode for ORR; the imm8 can be had via extraction from v32.
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*/
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static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
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{
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int i;
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for (i = 6; i > 0; i -= 2) {
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/* Mask out one byte we can add with ORR. */
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uint32_t tmp = v32 & ~(0xffu << (i * 4));
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if (is_shimm32(tmp, cmode, imm8) ||
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is_soimm32(tmp, cmode, imm8)) {
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break;
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}
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}
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return i;
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}
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/* Test if a constant matches the constraint.
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* TODO: define constraints for:
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*
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@ -1127,6 +1249,15 @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
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encode_vd(d) | encode_vn(n) | encode_vm(m));
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}
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static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
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int q, int op, int cmode, uint8_t imm8)
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{
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tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
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| (cmode << 8) | extract32(imm8, 0, 4)
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| (extract32(imm8, 4, 3) << 16)
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| (extract32(imm8, 7, 1) << 24));
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}
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static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
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TCGReg rd, TCGReg rn, int offset)
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{
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@ -2329,22 +2460,158 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
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tcg_out_movi32(s, COND_AL, ret, arg);
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}
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/* Type is always V128, with I64 elements. */
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static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
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{
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/* Move high element into place first. */
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/* VMOV Dd+1, Ds */
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tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
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/* Move low element into place; tcg_out_mov will check for nop. */
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tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
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}
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static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg rd, TCGReg rs)
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{
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g_assert_not_reached();
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int q = type - TCG_TYPE_V64;
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if (vece == MO_64) {
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if (type == TCG_TYPE_V128) {
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tcg_out_dup2_vec(s, rd, rs, rs);
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} else {
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tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
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}
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} else if (rs < TCG_REG_Q0) {
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int b = (vece == MO_8);
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int e = (vece == MO_16);
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tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
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encode_vn(rd) | (rs << 12));
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} else {
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int imm4 = 1 << vece;
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tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
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encode_vd(rd) | encode_vm(rs));
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}
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return true;
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}
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static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg rd, TCGReg base, intptr_t offset)
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{
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g_assert_not_reached();
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if (vece == MO_64) {
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tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
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if (type == TCG_TYPE_V128) {
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tcg_out_dup2_vec(s, rd, rd, rd);
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}
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} else {
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int q = type - TCG_TYPE_V64;
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tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
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rd, base, offset);
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}
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return true;
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}
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static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg rd, int64_t v64)
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{
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g_assert_not_reached();
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int q = type - TCG_TYPE_V64;
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int cmode, imm8, i;
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/* Test all bytes equal first. */
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if (vece == MO_8) {
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tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
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return;
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}
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/*
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* Test all bytes 0x00 or 0xff second. This can match cases that
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* might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
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*/
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for (i = imm8 = 0; i < 8; i++) {
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uint8_t byte = v64 >> (i * 8);
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if (byte == 0xff) {
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imm8 |= 1 << i;
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} else if (byte != 0) {
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goto fail_bytes;
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}
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}
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tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
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return;
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fail_bytes:
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/*
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* Tests for various replications. For each element width, if we
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* cannot find an expansion there's no point checking a larger
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* width because we already know by replication it cannot match.
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*/
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if (vece == MO_16) {
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uint16_t v16 = v64;
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if (is_shimm16(v16, &cmode, &imm8)) {
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tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
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return;
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}
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if (is_shimm16(~v16, &cmode, &imm8)) {
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tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
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return;
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}
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/*
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* Otherwise, all remaining constants can be loaded in two insns:
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* rd = v16 & 0xff, rd |= v16 & 0xff00.
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*/
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tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
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tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */
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return;
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}
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if (vece == MO_32) {
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uint32_t v32 = v64;
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if (is_shimm32(v32, &cmode, &imm8) ||
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is_soimm32(v32, &cmode, &imm8)) {
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tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
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return;
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}
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if (is_shimm32(~v32, &cmode, &imm8) ||
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is_soimm32(~v32, &cmode, &imm8)) {
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tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
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return;
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}
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/*
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* Restrict the set of constants to those we can load with
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* two instructions. Others we load from the pool.
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*/
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i = is_shimm32_pair(v32, &cmode, &imm8);
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if (i) {
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tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
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tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
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return;
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}
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i = is_shimm32_pair(~v32, &cmode, &imm8);
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if (i) {
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tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
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tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
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return;
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}
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}
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/*
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* As a last resort, load from the constant pool.
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*/
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if (!q || vece == MO_64) {
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new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
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/* VLDR Dd, [pc + offset] */
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tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
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if (q) {
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tcg_out_dup2_vec(s, rd, rd, rd);
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}
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} else {
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new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
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/* add tmp, pc, offset */
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
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tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
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}
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}
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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