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ppc patch queue for 2023-05-05:

Browse Source 
This queue includes fixes for ppc and spapr emulation, a build fix for
 the pseries machine and a new reviewer for ppc/spapr.
 
 We're also carrying a Coverity fix for the sm501 display.
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Merge tag 'pull-ppc-20230505' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-05-05:

This queue includes fixes for ppc and spapr emulation, a build fix for
the pseries machine and a new reviewer for ppc/spapr.

We're also carrying a Coverity fix for the sm501 display.

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# gpg: Signature made Fri 05 May 2023 05:26:00 PM BST
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20230505' of https://gitlab.com/danielhb/qemu:
  hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine
  tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
  tcg: ppc64: Fix mask generation for vextractdm
  MAINTAINERS: Adding myself in the list for ppc/spapr
  ppc: spapr: cleanup cr get/set with helpers.
  hw/display/sm501: Remove unneeded increment from loop

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-05 22:28:48 +01:00
commit 2149a21b2f
14 changed files with 90 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
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@ -1422,6 +1422,7 @@ M: Daniel Henrique Barboza <danielhb413@gmail.com>
R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
R: Harsh Prateek Bora <harshpb@linux.ibm.com>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/*/spapr*

2
hw/display/sm501.c
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@ -901,7 +901,7 @@ static void sm501_2d_operation(SM501State *s)
/* fallback when pixman failed or we don't want to call it */
uint8_t *d = s->local_mem + dst_base;
unsigned int x, y, i;
for (y = 0; y < height; y++, i += dst_pitch * bypp) {
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp) {
stn_he_p(&d[i], bypp, color);

2
hw/ppc/Kconfig
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@ -3,7 +3,7 @@ config PSERIES
imply PCI_DEVICES
imply TEST_DEVICES
imply VIRTIO_VGA
imply NVDIMM
select NVDIMM
select DIMM
select PCI
select SPAPR_VSCSI

18
hw/ppc/spapr_hcall.c
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@ -1566,8 +1566,6 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
struct kvmppc_hv_guest_state hv_state;
struct kvmppc_pt_regs *regs;
hwaddr len;
uint64_t cr;
int i;
if (spapr->nested_ptcr == 0) {
return H_NOT_AVAILABLE;
@ -1616,12 +1614,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
env->lr = regs->link;
env->ctr = regs->ctr;
cpu_write_xer(env, regs->xer);
cr = regs->ccr;
for (i = 7; i >= 0; i--) {
env->crf[i] = cr & 15;
cr >>= 4;
}
ppc_set_cr(env, regs->ccr);
env->msr = regs->msr;
env->nip = regs->nip;
@ -1698,8 +1691,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
struct kvmppc_hv_guest_state *hvstate;
struct kvmppc_pt_regs *regs;
hwaddr len;
uint64_t cr;
int i;
assert(spapr_cpu->in_nested);
@ -1757,12 +1748,7 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
regs->link = env->lr;
regs->ctr = env->ctr;
regs->xer = cpu_read_xer(env);
cr = 0;
for (i = 0; i < 8; i++) {
cr |= (env->crf[i] & 15) << (4 * (7 - i));
}
regs->ccr = cr;
regs->ccr = ppc_get_cr(env);
if (excp == POWERPC_EXCP_MCHECK ||
excp == POWERPC_EXCP_RESET ||

4
linux-user/elfload.c
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@ -961,9 +961,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
(*regs)[36] = tswapreg(env->lr);
(*regs)[37] = tswapreg(cpu_read_xer(env));
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
ccr |= env->crf[i] << (32 - ((i + 1) * 4));
}
ccr = ppc_get_cr(env);
(*regs)[38] = tswapreg(ccr);
}

9
linux-user/ppc/signal.c
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@ -243,9 +243,7 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
__put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
__put_user(cpu_read_xer(env), &frame->mc_gregs[TARGET_PT_XER]);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
ccr |= env->crf[i] << (32 - ((i + 1) * 4));
}
ccr = ppc_get_cr(env);
__put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
/* Save Altivec registers if necessary. */
@ -335,10 +333,7 @@ static void restore_user_regs(CPUPPCState *env,
cpu_write_xer(env, xer);
__get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
}
ppc_set_cr(env, ccr);
if (!sig) {
env->gpr[2] = save_r2;
}

17
target/ppc/cpu.c
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@ -67,6 +67,23 @@ uint32_t ppc_get_vscr(CPUPPCState *env)
return env->vscr | (sat << VSCR_SAT);
}
void ppc_set_cr(CPUPPCState *env, uint64_t cr)
{
for (int i = 7; i >= 0; i--) {
env->crf[i] = cr & 0xf;
cr >>= 4;
}
}
uint64_t ppc_get_cr(const CPUPPCState *env)
{
uint64_t cr = 0;
for (int i = 0; i < 8; i++) {
cr |= (env->crf[i] & 0xf) << (4 * (7 - i));
}
return cr;
}
/* GDBstub can read and write MSR... */
void ppc_store_msr(CPUPPCState *env, target_ulong value)
{

2
target/ppc/cpu.h
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@ -2773,6 +2773,8 @@ void dump_mmu(CPUPPCState *env);
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
uint32_t ppc_get_vscr(CPUPPCState *env);
void ppc_set_cr(CPUPPCState *env, uint64_t cr);
uint64_t ppc_get_cr(const CPUPPCState *env);
/*****************************************************************************/
/* Power management enable checks */

22
target/ppc/gdbstub.c
View File

@ -145,11 +145,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
break;
case 66:
{
uint32_t cr = 0;
int i;
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
uint32_t cr = ppc_get_cr(env);
gdb_get_reg32(buf, cr);
break;
}
@ -203,11 +199,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
break;
case 66 + 32:
{
uint32_t cr = 0;
int i;
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
uint32_t cr = ppc_get_cr(env);
gdb_get_reg32(buf, cr);
break;
}
@ -257,10 +249,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
case 66:
{
uint32_t cr = ldl_p(mem_buf);
int i;
for (i = 0; i < 8; i++) {
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
}
ppc_set_cr(env, cr);
break;
}
case 67:
@ -307,10 +296,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
case 66 + 32:
{
uint32_t cr = ldl_p(mem_buf);
int i;
for (i = 0; i < 8; i++) {
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
}
ppc_set_cr(env, cr);
break;
}
case 67 + 32:

13
target/ppc/kvm.c
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@ -927,10 +927,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
regs.gpr[i] = env->gpr[i];
}
regs.cr = 0;
for (i = 0; i < 8; i++) {
regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
}
regs.cr = ppc_get_cr(env);
ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
if (ret < 0) {
@ -1205,7 +1202,6 @@ int kvm_arch_get_registers(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
struct kvm_regs regs;
uint32_t cr;
int i, ret;
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
@ -1213,12 +1209,7 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
cr = regs.cr;
for (i = 7; i >= 0; i--) {
env->crf[i] = cr & 15;
cr >>= 4;
}
ppc_set_cr(env, regs.cr);
env->ctr = regs.ctr;
env->lr = regs.lr;
cpu_write_xer(env, regs.xer);

6
target/ppc/ppc-qmp-cmds.c
View File

@ -37,12 +37,8 @@ static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
{
CPUArchState *env = mon_get_cpu_env(mon);
unsigned int u;
int i;
u = 0;
for (i = 0; i < 8; i++) {
u |= env->crf[i] << (32 - (4 * (i + 1)));
}
u = ppc_get_cr(env);
return u;
}

2
target/ppc/translate/vmx-impl.c.inc
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@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
{
const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
mask = dup_const(vece, 1 << (elem_width - 1));
mask = dup_const(vece, 1ULL << (elem_width - 1));
uint64_t i, j;
TCGv_i64 lo, hi, t0, t1;

5
tests/tcg/ppc64/Makefile.target
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@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf
PPC64_TESTS += mffsce
ifneq ($(CROSS_CC_HAS_POWER10),)
PPC64_TESTS += byte_reverse sha512-vector
PPC64_TESTS += byte_reverse sha512-vector vector
endif
byte_reverse: CFLAGS += -mcpu=power10
run-byte_reverse: QEMU_OPTS+=-cpu POWER10
@ -31,6 +31,9 @@ sha512-vector: sha512.c
run-sha512-vector: QEMU_OPTS+=-cpu POWER10
vector: CFLAGS += -mcpu=power10 -I$(SRC_PATH)/include
run-vector: QEMU_OPTS += -cpu POWER10
PPC64_TESTS += signal_save_restore_xer
PPC64_TESTS += xxspltw

51
tests/tcg/ppc64/vector.c Normal file
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@ -0,0 +1,51 @@
#include <assert.h>
#include <stdint.h>
#include "qemu/compiler.h"
int main(void)
{
unsigned int result_wi;
vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0,
0, 0xFF, 0xFF};
vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF,
0, 0, 0xFFFF, 0xFFFF};
vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF};
vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0};
vector __uint128_t vbc_qi_src;
asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src));
#if HOST_BIG_ENDIAN
assert(result_wi == 0b1101111111000011);
#else
assert(result_wi == 0b1100001111111011);
#endif
asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src));
#if HOST_BIG_ENDIAN
assert(result_wi == 0b10010011);
#else
assert(result_wi == 0b11001001);
#endif
asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src));
#if HOST_BIG_ENDIAN
assert(result_wi == 0b0011);
#else
assert(result_wi == 0b1100);
#endif
asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src));
#if HOST_BIG_ENDIAN
assert(result_wi == 0b10);
#else
assert(result_wi == 0b01);
#endif
vbc_qi_src[0] = 0x1;
vbc_qi_src[0] = vbc_qi_src[0] << 127;
asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src));
assert(result_wi == 0b1);
return 0;
}