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ppc patch queue for 2022-12-21:

Browse Source 
This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC,
 the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of
 them for the e500 board).
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Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2022-12-21:

This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC,
the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of
them for the e500 board).

# gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu:
  target/ppc: Check DEXCR on hash{st, chk} instructions
  target/ppc: Implement the DEXCR and HDEXCR
  hw/ppc/e500: Move comment to more appropriate place
  hw/ppc/e500: Resolve variable shadowing
  hw/ppc/e500: Prefer local variable over qdev_get_machine()
  hw/ppc/virtex_ml507: Prefer local over global variable
  target/ppc/mmu_common: Fix table layout of "info tlb" HMP command
  target/ppc/mmu_common: Log which effective address had no TLB entry found
  hw/ppc/spapr: Reduce "vof.h" inclusion
  hw/ppc/vof: Do not include the full "cpu.h"
  target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h"
  hw/ppc/e500: Add Freescale eSDHC to e500plat
  hw/sd/sdhci: Support big endian SD host controller interfaces
  MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes'

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-12-21 18:08:09 +00:00
commit 222059a0fc
20 changed files with 220 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -276,7 +276,7 @@ R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
S: Odd Fixes
F: target/ppc/
F: hw/ppc/ppc.c
F: hw/ppc/ppc_booke.c
@ -402,7 +402,7 @@ M: Daniel Henrique Barboza <danielhb413@gmail.com>
R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
S: Maintained
S: Odd Fixes
F: target/ppc/kvm.c
S390 KVM CPUs
@ -1382,7 +1382,7 @@ R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
S: Odd Fixes
F: hw/*/spapr*
F: include/hw/*/spapr*
F: hw/*/xics*

13
docs/system/ppc/ppce500.rst
View File

@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
* Power-off functionality via one GPIO pin
* 1 Freescale MPC8xxx PCI host controller
* VirtIO devices via PCI bus
* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
* 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
Hardware configuration information
@ -180,3 +181,15 @@ as follows:
-kernel vmlinux \
-drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
-append "rootwait root=/dev/mtdblock0"
Alternatively, the root file system can also reside on an emulated SD card
whose size must again be a power of two:
.. code-block:: bash
$ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
-display none -serial stdio \
-kernel vmlinux \
-device sd-card,drive=mydrive \
-drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
-append "rootwait root=/dev/mmcblk0"

2
hw/ppc/Kconfig
View File

@ -128,10 +128,12 @@ config E500
select PFLASH_CFI01
select PLATFORM_BUS
select PPCE500_PCI
select SDHCI
select SERIAL
select MPC_I2C
select FDT_PPC
select DS1338
select UNIMP
config E500PLAT
bool

59
hw/ppc/e500.c
View File

@ -48,6 +48,8 @@
#include "hw/net/fsl_etsec/etsec.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
#include "hw/sd/sdhci.h"
#include "hw/misc/unimp.h"
#define EPAPR_MAGIC (0x45504150)
#define DTC_LOAD_PAD 0x1800000
@ -66,11 +68,14 @@
#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
#define MPC8544_PCI_REGS_SIZE 0x1000ULL
#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
#define MPC8544_UTIL_OFFSET 0xe0000ULL
#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
#define MPC8XXX_GPIO_IRQ 47
#define MPC8544_I2C_IRQ 43
#define MPC85XX_ESDHC_IRQ 72
#define RTC_REGS_OFFSET 0x68
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
g_free(i2c);
}
static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
{
hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
int irq = MPC85XX_ESDHC_IRQ;
g_autofree char *name = NULL;
name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
}
typedef struct PlatformDevtreeData {
void *fdt;
@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
dt_rtc_create(fdt, "i2c", "rtc");
/* sdhc */
if (pmc->has_esdhc) {
dt_sdhc_create(fdt, soc, mpic);
}
gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
MPC8544_UTIL_OFFSET);
@ -692,7 +717,6 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine,
kernel_base, kernel_size, true);
}
/* Create -kernel TLB entries for BookE. */
hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return 63 - clz64(size / KiB);
@ -723,6 +747,7 @@ static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
return (1ULL << 10 << tsize);
}
/* Create -kernel TLB entries for BookE. */
static void mmubooke_create_initial_mapping(CPUPPCState *env)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
@ -883,7 +908,7 @@ void ppce500_init(MachineState *machine)
bool kernel_as_payload;
hwaddr bios_entry = 0;
target_long payload_size;
struct boot_info *boot_info;
struct boot_info *boot_info = NULL;
int dt_size;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@ -938,7 +963,6 @@ void ppce500_init(MachineState *machine)
/* Register reset handler */
if (!i) {
/* Primary CPU */
struct boot_info *boot_info;
boot_info = g_new0(struct boot_info, 1);
qemu_register_reset(ppce500_cpu_reset, cpu);
env->load_info = boot_info;
@ -959,8 +983,7 @@ void ppce500_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, machine->ram);
dev = qdev_new("e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
OBJECT(dev));
object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
@ -982,7 +1005,8 @@ void ppce500_init(MachineState *machine)
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hd(1), DEVICE_BIG_ENDIAN);
}
/* I2C */
/* I2C */
dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
@ -992,6 +1016,26 @@ void ppce500_init(MachineState *machine)
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
/* eSDHC */
if (pmc->has_esdhc) {
create_unimplemented_device("esdhc",
pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET,
MPC85XX_ESDHC_REGS_SIZE);
/*
* Compatible with:
* - SD Host Controller Specification Version 2.0 Part A2
* (See MPC8569E Reference Manual)
*/
dev = qdev_new(TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
}
/* General Utility device */
dev = qdev_new("mpc8544-guts");
@ -1002,7 +1046,7 @@ void ppce500_init(MachineState *machine)
/* PCI */
dev = qdev_new("e500-pcihost");
object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
s = SYS_BUS_DEVICE(dev);
@ -1217,7 +1261,6 @@ void ppce500_init(MachineState *machine)
}
assert(dt_size < DTB_MAX_SIZE);
boot_info = env->load_info;
boot_info->entry = bios_entry;
boot_info->dt_base = dt_base;
boot_info->dt_size = dt_size;

1
hw/ppc/e500.h
View File

@ -27,6 +27,7 @@ struct PPCE500MachineClass {
int mpic_version;
bool has_mpc8xxx_gpio;
bool has_esdhc;
hwaddr platform_bus_base;
hwaddr platform_bus_size;
int platform_bus_first_irq;

1
hw/ppc/e500plat.c
View File

@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
pmc->fixup_devtree = e500plat_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
pmc->has_mpc8xxx_gpio = true;
pmc->has_esdhc = true;
pmc->platform_bus_base = 0xf00000000ULL;
pmc->platform_bus_size = 128 * MiB;
pmc->platform_bus_first_irq = 5;

1
hw/ppc/spapr.c
View File

@ -62,6 +62,7 @@
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_vio.h"
#include "hw/ppc/vof.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/spapr.h"
#include "hw/pci/msi.h"

2
hw/ppc/virtex_ml507.c
View File

@ -157,7 +157,7 @@ static int xilinx_load_device_tree(MachineState *machine,
int r;
const char *dtb_filename;
dtb_filename = current_machine->dtb;
dtb_filename = machine->dtb;
if (dtb_filename) {
fdt = load_device_tree(dtb_filename, &fdt_size);
if (!fdt) {

1
hw/sd/sdhci-internal.h
View File

@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate;
#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \

32
hw/sd/sdhci.c
View File

@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
value >> shift, value >> shift);
}
static const MemoryRegionOps sdhci_mmio_ops = {
static const MemoryRegionOps sdhci_mmio_le_ops = {
.read = sdhci_read,
.write = sdhci_write,
.valid = {
@ -1340,6 +1340,21 @@ static const MemoryRegionOps sdhci_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps sdhci_mmio_be_ops = {
.read = sdhci_read,
.write = sdhci_write,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.valid = {
.min_access_size = 1,
.max_access_size = 4,
.unaligned = false
},
.endianness = DEVICE_BIG_ENDIAN,
};
static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
@ -1367,8 +1382,6 @@ void sdhci_initfn(SDHCIState *s)
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
s->io_ops = &sdhci_mmio_ops;
}
void sdhci_uninitfn(SDHCIState *s)
@ -1384,10 +1397,23 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
switch (s->endianness) {
case DEVICE_LITTLE_ENDIAN:
s->io_ops = &sdhci_mmio_le_ops;
break;
case DEVICE_BIG_ENDIAN:
s->io_ops = &sdhci_mmio_be_ops;
break;
default:
error_setg(errp, "Incorrect endianness");
return;
}
sdhci_init_readonly_registers(s, errp);
if (*errp) {
return;
}
s->buf_maxsz = sdhci_get_fifolen(s);
s->fifo_buffer = g_malloc0(s->buf_maxsz);

3
include/hw/ppc/spapr.h
View File

@ -12,7 +12,6 @@
#include "hw/ppc/spapr_xive.h" /* For SpaprXive */
#include "hw/ppc/xics.h" /* For ICSState */
#include "hw/ppc/spapr_tpm_proxy.h"
#include "hw/ppc/vof.h"
struct SpaprVioBus;
struct SpaprPhbState;
@ -22,6 +21,8 @@ typedef struct SpaprEventLogEntry SpaprEventLogEntry;
typedef struct SpaprEventSource SpaprEventSource;
typedef struct SpaprPendingHpt SpaprPendingHpt;
typedef struct Vof Vof;
#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
#define SPAPR_ENTRY_POINT 0x100

2
include/hw/ppc/vof.h
View File

@ -9,7 +9,7 @@
#include "qom/object.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "cpu.h"
#include "exec/cpu-defs.h"
typedef struct Vof {
uint64_t top_addr; /* copied from rma_size */

1
include/hw/sd/sdhci.h
View File

@ -96,6 +96,7 @@ struct SDHCIState {
/* Configurable properties */
bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
uint32_t quirks;
uint8_t endianness;
uint8_t sd_spec_version;
uint8_t uhs_mode;
uint8_t vendor; /* For vendor specific functionality */

19
target/ppc/cpu.h
View File

@ -1068,6 +1068,21 @@ struct ppc_radix_page_info {
uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
};
/*****************************************************************************/
/* Dynamic Execution Control Register */
#define DEXCR_ASPECT(name, num) \
FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
DEXCR_ASPECT(SBHE, 0)
DEXCR_ASPECT(IBRTPD, 1)
DEXCR_ASPECT(SRAPD, 4)
DEXCR_ASPECT(NPHIE, 5)
DEXCR_ASPECT(PHIE, 6)
/*****************************************************************************/
/* The whole PowerPC CPU context */
@ -1674,9 +1689,11 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
#define SPR_UHDEXCR (0x1C7)
#define SPR_PTCR (0x1D0)
#define SPR_HASHKEYR (0x1D4)
#define SPR_HASHPKEYR (0x1D5)
#define SPR_HDEXCR (0x1D7)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
@ -1865,8 +1882,10 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_RCPU_L2U_RA2 (0x32A)
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_UDEXCR (0x32C)
#define SPR_TAR (0x32F)
#define SPR_ASDR (0x330)
#define SPR_DEXCR (0x33C)
#define SPR_IC (0x350)
#define SPR_VTB (0x351)
#define SPR_MMCRC (0x353)

25
target/ppc/cpu_init.c
View File

@ -5727,6 +5727,30 @@ static void register_power10_hash_sprs(CPUPPCState *env)
hashpkeyr_initial_value);
}
static void register_power10_dexcr_sprs(CPUPPCState *env)
{
spr_register(env, SPR_DEXCR, "DEXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
spr_register(env, SPR_UDEXCR, "DEXCR",
&spr_read_dexcr_ureg, SPR_NOACCESS,
&spr_read_dexcr_ureg, SPR_NOACCESS,
0);
spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
spr_register(env, SPR_UHDEXCR, "HDEXCR",
&spr_read_dexcr_ureg, SPR_NOACCESS,
&spr_read_dexcr_ureg, SPR_NOACCESS,
0);
}
/*
* Initialize PMU counter overflow timers for Power8 and
* newer Power chips when using TCG.
@ -6402,6 +6426,7 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power8_rpr_sprs(env);
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
register_power10_dexcr_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,

58
target/ppc/excp_helper.c
View File

@ -2902,29 +2902,57 @@ static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
return stage1_h ^ stage1_l;
}
static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra,
target_ulong rb, uint64_t key, bool store)
{
uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash;
if (store) {
cpu_stq_data_ra(env, ea, calculated_hash, GETPC());
} else {
loaded_hash = cpu_ldq_data_ra(env, ea, GETPC());
if (loaded_hash != calculated_hash) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_TRAP, GETPC());
}
}
}
#include "qemu/guest-random.h"
#define HELPER_HASH(op, key, store) \
#ifdef TARGET_PPC64
#define HELPER_HASH(op, key, store, dexcr_aspect) \
void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
target_ulong rb) \
{ \
uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash; \
\
if (store) { \
cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); \
} else { \
loaded_hash = cpu_ldq_data_ra(env, ea, GETPC()); \
if (loaded_hash != calculated_hash) { \
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, \
POWERPC_EXCP_TRAP, GETPC()); \
} \
if (env->msr & R_MSR_PR_MASK) { \
if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
return; \
} else if (!(env->msr & R_MSR_HV_MASK)) { \
if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
return; \
} else if (!(env->msr & R_MSR_S_MASK)) { \
if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
return; \
} \
\
do_hash(env, ea, ra, rb, key, store); \
}
#else
#define HELPER_HASH(op, key, store, dexcr_aspect) \
void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
target_ulong rb) \
{ \
do_hash(env, ea, ra, rb, key, store); \
}
#endif /* TARGET_PPC64 */
HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true)
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false)
HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false)
HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
#endif /* CONFIG_TCG */
#if !defined(CONFIG_USER_ONLY)

3
target/ppc/kvm_ppc.h
View File

@ -9,6 +9,9 @@
#ifndef KVM_PPC_H
#define KVM_PPC_H
#include "exec/hwaddr.h"
#include "cpu.h"
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
#ifdef CONFIG_KVM

5
target/ppc/mmu_common.c
View File

@ -811,7 +811,8 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
}
}
qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__);
qemu_log_mask(CPU_LOG_MMU, "%s: No TLB entry found for effective address "
"0x" TARGET_FMT_lx "\n", __func__, address);
return -1;
found_tlb:
@ -979,7 +980,7 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
pa = entry->mas7_3 & ~(size - 1);
qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
"U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
" U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
(uint64_t)ea, (uint64_t)pa,
book3e_tsize_to_str[tsize],
(entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,

1
target/ppc/spr_common.h
View File

@ -195,6 +195,7 @@ void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn);
void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn);
void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn);
#endif
void register_low_BATs(CPUPPCState *env);

19
target/ppc/translate.c
View File

@ -1249,6 +1249,25 @@ void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_write_prev_upper32(ctx, sprn, gprn);
}
void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
{
TCGv t0 = tcg_temp_new();
/*
* Access to the (H)DEXCR in problem state is done using separated
* SPR indexes which are 16 below the SPR indexes which have full
* access to the (H)DEXCR in privileged state. Problem state can
* only read bits 32:63, bits 0:31 return 0.
*
* See section 9.3.1-9.3.2 of PowerISA v3.1B
*/
gen_load_spr(t0, sprn + 16);
tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
tcg_temp_free(t0);
}
#endif
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \