hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
Add the CPU interface registers which deal with acknowledging and dismissing interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
b1a0eb777d
commit
227a865366
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@ -219,6 +219,297 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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gicv3_cpuif_update(cs);
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}
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static void icc_activate_irq(GICv3CPUState *cs, int irq)
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{
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/* Move the interrupt from the Pending state to Active, and update
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* the Active Priority Registers
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*/
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uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp);
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int prio = cs->hppi.prio & mask;
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int aprbit = prio >> 1;
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int regno = aprbit / 32;
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int regbit = aprbit % 32;
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cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit);
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if (irq < GIC_INTERNAL) {
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cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
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cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
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gicv3_redist_update(cs);
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} else {
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gicv3_gicd_active_set(cs->gic, irq);
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gicv3_gicd_pending_clear(cs->gic, irq);
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gicv3_update(cs->gic, irq, 1);
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}
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}
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static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env)
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{
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/* Return the highest priority pending interrupt register value
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* for group 0.
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*/
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bool irq_is_secure;
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if (cs->hppi.prio == 0xff) {
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return INTID_SPURIOUS;
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}
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/* Check whether we can return the interrupt or if we should return
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* a special identifier, as per the CheckGroup0ForSpecialIdentifiers
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* pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
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* is always zero.)
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*/
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irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
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(cs->hppi.grp != GICV3_G1NS));
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if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) {
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return INTID_SPURIOUS;
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}
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if (irq_is_secure && !arm_is_secure(env)) {
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/* Secure interrupts not visible to Nonsecure */
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return INTID_SPURIOUS;
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}
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if (cs->hppi.grp != GICV3_G0) {
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/* Indicate to EL3 that there's a Group 1 interrupt for the other
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* state pending.
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*/
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return irq_is_secure ? INTID_SECURE : INTID_NONSECURE;
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}
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return cs->hppi.irq;
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}
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static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env)
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{
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/* Return the highest priority pending interrupt register value
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* for group 1.
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*/
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bool irq_is_secure;
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if (cs->hppi.prio == 0xff) {
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return INTID_SPURIOUS;
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}
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/* Check whether we can return the interrupt or if we should return
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* a special identifier, as per the CheckGroup1ForSpecialIdentifiers
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* pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
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* is always zero.)
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*/
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irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
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(cs->hppi.grp != GICV3_G1NS));
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if (cs->hppi.grp == GICV3_G0) {
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/* Group 0 interrupts not visible via HPPIR1 */
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return INTID_SPURIOUS;
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}
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if (irq_is_secure) {
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if (!arm_is_secure(env)) {
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/* Secure interrupts not visible in Non-secure */
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return INTID_SPURIOUS;
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}
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} else if (!arm_is_el3_or_mon(env) && arm_is_secure(env)) {
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/* Group 1 non-secure interrupts not visible in Secure EL1 */
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return INTID_SPURIOUS;
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}
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return cs->hppi.irq;
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}
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static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t intid;
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if (!icc_hppi_can_preempt(cs)) {
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intid = INTID_SPURIOUS;
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} else {
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intid = icc_hppir0_value(cs, env);
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}
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if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
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icc_activate_irq(cs, intid);
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}
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trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid);
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return intid;
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}
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static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t intid;
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if (!icc_hppi_can_preempt(cs)) {
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intid = INTID_SPURIOUS;
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} else {
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intid = icc_hppir1_value(cs, env);
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}
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if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
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icc_activate_irq(cs, intid);
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}
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trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid);
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return intid;
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}
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static void icc_drop_prio(GICv3CPUState *cs, int grp)
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{
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/* Drop the priority of the currently active interrupt in
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* the specified group.
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*
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* Note that we can guarantee (because of the requirement to nest
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* ICC_IAR reads [which activate an interrupt and raise priority]
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* with ICC_EOIR writes [which drop the priority for the interrupt])
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* that the interrupt we're being called for is the highest priority
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* active interrupt, meaning that it has the lowest set bit in the
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* APR registers.
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*
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* If the guest does not honour the ordering constraints then the
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* behaviour of the GIC is UNPREDICTABLE, which for us means that
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* the values of the APR registers might become incorrect and the
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* running priority will be wrong, so interrupts that should preempt
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* might not do so, and interrupts that should not preempt might do so.
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*/
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int i;
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for (i = 0; i < ARRAY_SIZE(cs->icc_apr[grp]); i++) {
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uint64_t *papr = &cs->icc_apr[grp][i];
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if (!*papr) {
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continue;
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}
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/* Clear the lowest set bit */
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*papr &= *papr - 1;
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break;
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}
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/* running priority change means we need an update for this cpu i/f */
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gicv3_cpuif_update(cs);
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}
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static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs)
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{
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/* Return true if we should split priority drop and interrupt
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* deactivation, ie whether the relevant EOIMode bit is set.
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*/
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if (arm_is_el3_or_mon(env)) {
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return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3;
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}
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if (arm_is_secure_below_el3(env)) {
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return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE;
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} else {
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return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE;
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}
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}
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static int icc_highest_active_group(GICv3CPUState *cs)
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{
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/* Return the group with the highest priority active interrupt.
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* We can do this by just comparing the APRs to see which one
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* has the lowest set bit.
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* (If more than one group is active at the same priority then
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* we're in UNPREDICTABLE territory.)
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*/
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int i;
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for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
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int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]);
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int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]);
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int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]);
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if (g1nsctz < g0ctz && g1nsctz < g1ctz) {
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return GICV3_G1NS;
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}
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if (g1ctz < g0ctz) {
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return GICV3_G1;
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}
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if (g0ctz < 32) {
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return GICV3_G0;
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}
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}
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/* No set active bits? UNPREDICTABLE; return -1 so the caller
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* ignores the spurious EOI attempt.
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*/
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return -1;
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}
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static void icc_deactivate_irq(GICv3CPUState *cs, int irq)
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{
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if (irq < GIC_INTERNAL) {
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cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0);
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gicv3_redist_update(cs);
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} else {
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gicv3_gicd_active_clear(cs->gic, irq);
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gicv3_update(cs->gic, irq, 1);
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}
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}
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static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* End of Interrupt */
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GICv3CPUState *cs = icc_cs_from_env(env);
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int irq = value & 0xffffff;
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int grp;
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trace_gicv3_icc_eoir_write(gicv3_redist_affid(cs), value);
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if (ri->crm == 8) {
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/* EOIR0 */
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grp = GICV3_G0;
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} else {
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/* EOIR1 */
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if (arm_is_secure(env)) {
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grp = GICV3_G1;
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} else {
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grp = GICV3_G1NS;
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}
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}
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if (irq >= cs->gic->num_irq) {
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/* This handles two cases:
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* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
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* to the GICC_EOIR, the GIC ignores that write.
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* 2. If software writes the number of a non-existent interrupt
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* this must be a subcase of "value written does not match the last
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* valid interrupt value read from the Interrupt Acknowledge
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* register" and so this is UNPREDICTABLE. We choose to ignore it.
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*/
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return;
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}
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if (icc_highest_active_group(cs) != grp) {
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return;
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}
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icc_drop_prio(cs, grp);
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if (!icc_eoi_split(env, cs)) {
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/* Priority drop and deactivate not split: deactivate irq now */
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icc_deactivate_irq(cs, irq);
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}
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}
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static uint64_t icc_hppir0_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value = icc_hppir0_value(cs, env);
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trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static uint64_t icc_hppir1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value = icc_hppir1_value(cs, env);
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trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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@ -331,6 +622,104 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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gicv3_cpuif_update(cs);
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}
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static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* Deactivate interrupt */
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GICv3CPUState *cs = icc_cs_from_env(env);
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int irq = value & 0xffffff;
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bool irq_is_secure, single_sec_state, irq_is_grp0;
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bool route_fiq_to_el3, route_irq_to_el3, route_fiq_to_el2, route_irq_to_el2;
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trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value);
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if (irq >= cs->gic->num_irq) {
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/* Also catches special interrupt numbers and LPIs */
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return;
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}
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if (!icc_eoi_split(env, cs)) {
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return;
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}
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int grp = gicv3_irq_group(cs->gic, cs, irq);
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single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS;
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irq_is_secure = !single_sec_state && (grp != GICV3_G1NS);
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irq_is_grp0 = grp == GICV3_G0;
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/* Check whether we're allowed to deactivate this interrupt based
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* on its group and the current CPU state.
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* These checks are laid out to correspond to the spec's pseudocode.
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*/
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route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ;
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route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ;
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/* No need to include !IsSecure in route_*_to_el2 as it's only
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* tested in cases where we know !IsSecure is true.
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*/
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route_fiq_to_el2 = env->cp15.hcr_el2 & HCR_FMO;
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route_irq_to_el2 = env->cp15.hcr_el2 & HCR_FMO;
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switch (arm_current_el(env)) {
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case 3:
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break;
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case 2:
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if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
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break;
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}
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if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
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break;
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}
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return;
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case 1:
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if (!arm_is_secure_below_el3(env)) {
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if (single_sec_state && irq_is_grp0 &&
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!route_fiq_to_el3 && !route_fiq_to_el2) {
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break;
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}
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if (!irq_is_secure && !irq_is_grp0 &&
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!route_irq_to_el3 && !route_irq_to_el2) {
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break;
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}
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} else {
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if (irq_is_grp0 && !route_fiq_to_el3) {
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break;
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}
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if (!irq_is_grp0 &&
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(!irq_is_secure || !single_sec_state) &&
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!route_irq_to_el3) {
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break;
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}
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}
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return;
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default:
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g_assert_not_reached();
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}
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icc_deactivate_irq(cs, irq);
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}
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static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int prio = icc_highest_active_prio(cs);
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if (arm_feature(env, ARM_FEATURE_EL3) &&
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!arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) {
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/* NS GIC access and Group 0 is inaccessible to NS */
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if (prio & 0x80) {
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/* NS mustn't see priorities in the Secure half of the range */
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prio = 0;
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} else if (prio != 0xff) {
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/* Non-idle priority: show the Non-secure view of it */
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prio = (prio << 1) & 0xff;
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}
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}
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trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio);
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return prio;
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}
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static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs,
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uint64_t value, int grp, bool ns)
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{
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@ -698,6 +1087,24 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
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*/
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.resetfn = icc_reset,
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},
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{ .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0,
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.type = ARM_CP_IO | ARM_CP_NO_RAW,
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.access = PL1_R, .accessfn = gicv3_fiq_access,
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.readfn = icc_iar0_read,
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},
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{ .name = "ICC_EOIR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
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.type = ARM_CP_IO | ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = gicv3_fiq_access,
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.writefn = icc_eoir_write,
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},
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{ .name = "ICC_HPPIR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2,
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.type = ARM_CP_IO | ARM_CP_NO_RAW,
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.access = PL1_R, .accessfn = gicv3_fiq_access,
|
||||
.readfn = icc_hppir0_read,
|
||||
},
|
||||
{ .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
|
|
@ -762,6 +1169,18 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
|
|||
.readfn = icc_ap_read,
|
||||
.writefn = icc_ap_write,
|
||||
},
|
||||
{ .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
|
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.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
.access = PL1_W, .accessfn = gicv3_irqfiq_access,
|
||||
.writefn = icc_dir_write,
|
||||
},
|
||||
{ .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
.access = PL1_R, .accessfn = gicv3_irqfiq_access,
|
||||
.readfn = icc_rpr_read,
|
||||
},
|
||||
{ .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
|
|
@ -798,6 +1217,24 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
|
|||
.access = PL1_W, .accessfn = gicv3_irqfiq_access,
|
||||
.writefn = icc_sgi0r_write,
|
||||
},
|
||||
{ .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
.access = PL1_R, .accessfn = gicv3_irq_access,
|
||||
.readfn = icc_iar1_read,
|
||||
},
|
||||
{ .name = "ICC_EOIR1_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
.access = PL1_W, .accessfn = gicv3_irq_access,
|
||||
.writefn = icc_eoir_write,
|
||||
},
|
||||
{ .name = "ICC_HPPIR1_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 2,
|
||||
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
||||
.access = PL1_R, .accessfn = gicv3_irq_access,
|
||||
.readfn = icc_hppir1_read,
|
||||
},
|
||||
/* This register is banked */
|
||||
{ .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3,
|
||||
|
|
|
|||
|
|
@ -159,6 +159,11 @@
|
|||
#define ICC_CTLR_EL3_A3V (1U << 15)
|
||||
#define ICC_CTLR_EL3_NDS (1U << 17)
|
||||
|
||||
/* Special interrupt IDs */
|
||||
#define INTID_SECURE 1020
|
||||
#define INTID_NONSECURE 1021
|
||||
#define INTID_SPURIOUS 1023
|
||||
|
||||
/* Functions internal to the emulated GICv3 */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2184,6 +2184,13 @@ gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 write c
|
|||
gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) "GICv3 CPU i/f %x HPPI update: irq %d group %d prio %d"
|
||||
gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f %x HPPI update: setting FIQ %d IRQ %d"
|
||||
gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) "GICv3 CPU i/f %x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x"
|
||||
gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_eoir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR write cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_DIR write cpu %x value 0x%" PRIx64
|
||||
gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_RPR read cpu %x value 0x%" PRIx64
|
||||
|
||||
# hw/intc/arm_gicv3_dist.c
|
||||
gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
|
||||
|
|
|
|||
Loading…
Reference in New Issue