arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR) Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -879,6 +879,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
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val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
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return val;
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return val;
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case 0xd24: /* System Handler Control and State (SHCSR) */
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case 0xd24: /* System Handler Control and State (SHCSR) */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
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goto bad_offset;
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}
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val = 0;
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val = 0;
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if (attrs.secure) {
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if (attrs.secure) {
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if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
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if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
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@ -1312,6 +1315,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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cpu->env.v7m.scr[attrs.secure] = value;
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cpu->env.v7m.scr[attrs.secure] = value;
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break;
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break;
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case 0xd14: /* Configuration Control. */
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case 0xd14: /* Configuration Control. */
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if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
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goto bad_offset;
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}
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/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
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/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
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value &= (R_V7M_CCR_STKALIGN_MASK |
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value &= (R_V7M_CCR_STKALIGN_MASK |
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R_V7M_CCR_BFHFNMIGN_MASK |
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R_V7M_CCR_BFHFNMIGN_MASK |
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@ -1336,6 +1343,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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cpu->env.v7m.ccr[attrs.secure] = value;
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cpu->env.v7m.ccr[attrs.secure] = value;
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break;
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break;
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case 0xd24: /* System Handler Control and State (SHCSR) */
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case 0xd24: /* System Handler Control and State (SHCSR) */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
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goto bad_offset;
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}
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if (attrs.secure) {
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if (attrs.secure) {
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s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
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s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
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/* Secure HardFault active bit cannot be written */
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/* Secure HardFault active bit cannot be written */
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@ -231,6 +231,10 @@ static void arm_cpu_reset(CPUState *s)
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env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
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env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
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env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
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env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
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}
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}
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if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
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env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
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env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
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}
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/* Unlike A/R profile, M profile defines the reset LR value */
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/* Unlike A/R profile, M profile defines the reset LR value */
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env->regs[14] = 0xffffffff;
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env->regs[14] = 0xffffffff;
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@ -10710,13 +10710,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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env->v7m.primask[M_REG_NS] = val & 1;
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env->v7m.primask[M_REG_NS] = val & 1;
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return;
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return;
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case 0x91: /* BASEPRI_NS */
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case 0x91: /* BASEPRI_NS */
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if (!env->v7m.secure) {
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if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
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return;
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return;
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}
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}
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env->v7m.basepri[M_REG_NS] = val & 0xff;
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env->v7m.basepri[M_REG_NS] = val & 0xff;
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return;
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return;
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case 0x93: /* FAULTMASK_NS */
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case 0x93: /* FAULTMASK_NS */
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if (!env->v7m.secure) {
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if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
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return;
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return;
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}
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}
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env->v7m.faultmask[M_REG_NS] = val & 1;
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env->v7m.faultmask[M_REG_NS] = val & 1;
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@ -10800,9 +10800,15 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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env->v7m.primask[env->v7m.secure] = val & 1;
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env->v7m.primask[env->v7m.secure] = val & 1;
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break;
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break;
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case 17: /* BASEPRI */
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case 17: /* BASEPRI */
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if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
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goto bad_reg;
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}
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env->v7m.basepri[env->v7m.secure] = val & 0xff;
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env->v7m.basepri[env->v7m.secure] = val & 0xff;
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break;
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break;
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case 18: /* BASEPRI_MAX */
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case 18: /* BASEPRI_MAX */
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if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
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goto bad_reg;
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}
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val &= 0xff;
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val &= 0xff;
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if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
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if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
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|| env->v7m.basepri[env->v7m.secure] == 0)) {
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|| env->v7m.basepri[env->v7m.secure] == 0)) {
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@ -10810,6 +10816,9 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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}
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}
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break;
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break;
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case 19: /* FAULTMASK */
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case 19: /* FAULTMASK */
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if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
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goto bad_reg;
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}
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env->v7m.faultmask[env->v7m.secure] = val & 1;
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env->v7m.faultmask[env->v7m.secure] = val & 1;
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break;
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break;
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case 20: /* CONTROL */
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case 20: /* CONTROL */
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