OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Add set/clear_pstate_bits, share gen_ss_advance 

We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-03-01 12:04:56 -08:00 committed by Peter Maydell
parent ff730e9666
commit 22ac3c4964
5 changed files with 34 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/arm/helper.h
View File

@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
DEF_HELPER_1(clear_pstate_ss, void, env)
DEF_HELPER_2(get_r13_banked, i32, env, i32)
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)

5
target/arm/op_helper.c
View File

@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
return res;
}
void HELPER(clear_pstate_ss)(CPUARMState *env)
{
env->pstate &= ~PSTATE_SS;
}
void HELPER(pre_hvc)(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);

11
target/arm/translate-a64.c
View File

@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
s->base.is_jmp = DISAS_NORETURN;
}
static void gen_ss_advance(DisasContext *s)
{
/* If the singlestep state is Active-not-pending, advance to
* Active-pending.
*/
if (s->ss_active) {
s->pstate_ss = 0;
gen_helper_clear_pstate_ss(cpu_env);
}
}
static void gen_step_complete_exception(DisasContext *s)
{
/* We just completed step of an insn. Move from Active-not-pending

11
target/arm/translate.c
View File

@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
tcg_temp_free_i32(tcg_excp);
}
static void gen_ss_advance(DisasContext *s)
{
/* If the singlestep state is Active-not-pending, advance to
* Active-pending.
*/
if (s->ss_active) {
s->pstate_ss = 0;
gen_helper_clear_pstate_ss(cpu_env);
}
}
static void gen_step_complete_exception(DisasContext *s)
{
/* We just completed step of an insn. Move from Active-not-pending

34
target/arm/translate.h
View File

@ -202,6 +202,40 @@ static inline TCGv_i32 get_ahp_flag(void)
return ret;
}
/* Set bits within PSTATE. */
static inline void set_pstate_bits(uint32_t bits)
{
TCGv_i32 p = tcg_temp_new_i32();
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(p, p, bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(p);
}
/* Clear bits within PSTATE. */
static inline void clear_pstate_bits(uint32_t bits)
{
TCGv_i32 p = tcg_temp_new_i32();
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(p, p, ~bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(p);
}
/* If the singlestep state is Active-not-pending, advance to Active-pending. */
static inline void gen_ss_advance(DisasContext *s)
{
if (s->ss_active) {
s->pstate_ss = 0;
clear_pstate_bits(PSTATE_SS);
}
}
/* Vector operations shared between ARM and AArch64. */
extern const GVecGen3 bsl_op;