target/arm: Use tcg_constant in translate-vfp.c
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
aa5b0b29b1
commit
230c90ceb4
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@ -180,8 +180,7 @@ static void gen_update_fp_context(DisasContext *s)
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gen_helper_vfp_set_fpscr(cpu_env, fpscr);
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tcg_temp_free_i32(fpscr);
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if (dc_isar_feature(aa32_mve, s)) {
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TCGv_i32 z32 = tcg_const_i32(0);
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store_cpu_field(z32, v7m.vpr);
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store_cpu_field(tcg_constant_i32(0), v7m.vpr);
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}
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/*
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* We just updated the FPSCR and VPR. Some of this state is cached
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@ -317,7 +316,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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TCGv_i64 frn, frm, dest;
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TCGv_i64 tmp, zero, zf, nf, vf;
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zero = tcg_const_i64(0);
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zero = tcg_constant_i64(0);
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frn = tcg_temp_new_i64();
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frm = tcg_temp_new_i64();
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@ -335,27 +334,22 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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vfp_load_reg64(frm, rm);
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switch (a->cc) {
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case 0: /* eq: Z */
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tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
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frn, frm);
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tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, frn, frm);
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break;
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case 1: /* vs: V */
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tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
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frn, frm);
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tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, frn, frm);
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break;
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case 2: /* ge: N == V -> N ^ V == 0 */
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tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(tmp, vf, nf);
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tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
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frn, frm);
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tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, frn, frm);
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tcg_temp_free_i64(tmp);
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break;
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case 3: /* gt: !Z && N == V */
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tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
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frn, frm);
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tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, frn, frm);
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tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(tmp, vf, nf);
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tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
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dest, frm);
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tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, dest, frm);
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tcg_temp_free_i64(tmp);
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break;
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}
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@ -367,13 +361,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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tcg_temp_free_i64(zf);
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tcg_temp_free_i64(nf);
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tcg_temp_free_i64(vf);
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tcg_temp_free_i64(zero);
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} else {
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TCGv_i32 frn, frm, dest;
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TCGv_i32 tmp, zero;
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zero = tcg_const_i32(0);
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zero = tcg_constant_i32(0);
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frn = tcg_temp_new_i32();
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frm = tcg_temp_new_i32();
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@ -382,27 +374,22 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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vfp_load_reg32(frm, rm);
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switch (a->cc) {
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case 0: /* eq: Z */
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tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
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frn, frm);
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tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm);
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break;
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case 1: /* vs: V */
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tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
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frn, frm);
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tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, frn, frm);
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break;
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case 2: /* ge: N == V -> N ^ V == 0 */
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tmp = tcg_temp_new_i32();
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tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
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frn, frm);
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tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm);
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tcg_temp_free_i32(tmp);
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break;
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case 3: /* gt: !Z && N == V */
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tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
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frn, frm);
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tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, frn, frm);
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tmp = tcg_temp_new_i32();
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tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
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tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
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dest, frm);
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tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm);
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tcg_temp_free_i32(tmp);
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break;
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}
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@ -414,8 +401,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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tcg_temp_free_i32(frn);
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tcg_temp_free_i32(frm);
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tcg_temp_free_i32(dest);
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tcg_temp_free_i32(zero);
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}
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return true;
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@ -547,7 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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fpst = fpstatus_ptr(FPST_FPCR);
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}
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tcg_shift = tcg_const_i32(0);
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tcg_shift = tcg_constant_i32(0);
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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@ -595,8 +580,6 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
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tcg_temp_free_i32(tcg_rmode);
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tcg_temp_free_i32(tcg_shift);
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tcg_temp_free_ptr(fpst);
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return true;
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@ -850,15 +833,11 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
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case ARM_VFP_MVFR2:
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case ARM_VFP_FPSID:
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if (s->current_el == 1) {
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TCGv_i32 tcg_reg, tcg_rt;
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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tcg_reg = tcg_const_i32(a->reg);
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tcg_rt = tcg_const_i32(a->rt);
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gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg);
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tcg_temp_free_i32(tcg_reg);
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tcg_temp_free_i32(tcg_rt);
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gen_helper_check_hcr_el2_trap(cpu_env,
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tcg_constant_i32(a->rt),
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tcg_constant_i32(a->reg));
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}
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/* fall through */
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case ARM_VFP_FPEXC:
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@ -2388,8 +2367,6 @@ MAKE_VFM_TRANS_FNS(dp)
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static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
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{
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TCGv_i32 fd;
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if (!dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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@ -2402,9 +2379,7 @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
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return true;
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}
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fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
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vfp_store_reg32(fd, a->vd);
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tcg_temp_free_i32(fd);
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vfp_store_reg32(tcg_constant_i32(vfp_expand_imm(MO_16, a->imm)), a->vd);
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return true;
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}
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@ -2440,7 +2415,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
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}
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}
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fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
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fd = tcg_constant_i32(vfp_expand_imm(MO_32, a->imm));
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for (;;) {
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vfp_store_reg32(fd, vd);
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@ -2454,7 +2429,6 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
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vd = vfp_advance_sreg(vd, delta_d);
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}
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tcg_temp_free_i32(fd);
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return true;
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}
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@ -2495,7 +2469,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
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}
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}
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fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
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fd = tcg_constant_i64(vfp_expand_imm(MO_64, a->imm));
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for (;;) {
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vfp_store_reg64(fd, vd);
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@ -2509,7 +2483,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
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vd = vfp_advance_dreg(vd, delta_d);
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}
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tcg_temp_free_i64(fd);
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return true;
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}
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@ -3294,7 +3267,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
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vfp_load_reg32(vd, a->vd);
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fpst = fpstatus_ptr(FPST_FPCR_F16);
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shift = tcg_const_i32(frac_bits);
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shift = tcg_constant_i32(frac_bits);
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/* Switch on op:U:sx bits */
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switch (a->opc) {
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@ -3328,7 +3301,6 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
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vfp_store_reg32(vd, a->vd);
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tcg_temp_free_i32(vd);
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tcg_temp_free_i32(shift);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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@ -3353,7 +3325,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
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vfp_load_reg32(vd, a->vd);
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fpst = fpstatus_ptr(FPST_FPCR);
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shift = tcg_const_i32(frac_bits);
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shift = tcg_constant_i32(frac_bits);
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/* Switch on op:U:sx bits */
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switch (a->opc) {
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@ -3387,7 +3359,6 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
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vfp_store_reg32(vd, a->vd);
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tcg_temp_free_i32(vd);
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tcg_temp_free_i32(shift);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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@ -3418,7 +3389,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
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vfp_load_reg64(vd, a->vd);
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fpst = fpstatus_ptr(FPST_FPCR);
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shift = tcg_const_i32(frac_bits);
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shift = tcg_constant_i32(frac_bits);
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/* Switch on op:U:sx bits */
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switch (a->opc) {
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@ -3452,7 +3423,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
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vfp_store_reg64(vd, a->vd);
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tcg_temp_free_i64(vd);
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tcg_temp_free_i32(shift);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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