tcg/s390x: Remove DISTINCT_OPERANDS facility check
The distinct-operands facility is bundled into facility 45, along with load-on-condition. We are checking this at startup. Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there is no space savings for avoiding the distinct-operands insn. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -2218,8 +2218,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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if (const_args[2]) {
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a2 = -a2;
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goto do_addi_64;
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, SGR, a0, a2);
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} else {
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tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
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}
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@ -2230,8 +2228,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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if (const_args[2]) {
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tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
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tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, NGR, args[0], args[2]);
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} else {
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tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
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}
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@ -2241,8 +2237,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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if (const_args[2]) {
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tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
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tgen_ori(s, TCG_TYPE_I64, a0, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, OGR, a0, a2);
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} else {
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tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
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}
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@ -2252,8 +2246,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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if (const_args[2]) {
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tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
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tgen_xori(s, TCG_TYPE_I64, a0, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, XGR, a0, a2);
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} else {
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tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
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}
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@ -2926,9 +2918,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_or_i64:
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case INDEX_op_xor_i32:
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case INDEX_op_xor_i64:
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return (HAVE_FACILITY(DISTINCT_OPS)
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? C_O1_I2(r, r, ri)
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: C_O1_I2(r, 0, ri));
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return C_O1_I2(r, r, ri);
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case INDEX_op_mul_i32:
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return C_O1_I2(r, 0, ri);
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@ -2938,9 +2928,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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return (HAVE_FACILITY(DISTINCT_OPS)
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? C_O1_I2(r, r, ri)
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: C_O1_I2(r, 0, ri));
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return C_O1_I2(r, r, ri);
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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@ -62,7 +62,6 @@ typedef enum TCGReg {
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/* Facilities that are checked at runtime. */
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#define FACILITY_DISTINCT_OPS 45
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#define FACILITY_LOAD_ON_COND2 53
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#define FACILITY_VECTOR 129
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#define FACILITY_VECTOR_ENH1 135
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