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tcg/s390x: Remove DISTINCT_OPERANDS facility check

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The distinct-operands facility is bundled into facility 45,
along with load-on-condition.  We are checking this at startup.
Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there
is no space savings for avoiding the distinct-operands insn.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-12-07 17:50:15 +00:00
parent e62d5752f5
commit 238da1c942
2 changed files with 2 additions and 15 deletions
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16
tcg/s390x/tcg-target.c.inc
View File

@ -2218,8 +2218,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (const_args[2]) { if (const_args[2]) {
a2 = -a2; a2 = -a2;
goto do_addi_64; goto do_addi_64;
} else if (a0 == a1) {
tcg_out_insn(s, RRE, SGR, a0, a2);
} else { } else {
tcg_out_insn(s, RRF, SGRK, a0, a1, a2); tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
} }
@ -2230,8 +2228,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (const_args[2]) { if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
} else if (a0 == a1) {
tcg_out_insn(s, RRE, NGR, args[0], args[2]);
} else { } else {
tcg_out_insn(s, RRF, NGRK, a0, a1, a2); tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
} }
@ -2241,8 +2237,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (const_args[2]) { if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_ori(s, TCG_TYPE_I64, a0, a2); tgen_ori(s, TCG_TYPE_I64, a0, a2);
} else if (a0 == a1) {
tcg_out_insn(s, RRE, OGR, a0, a2);
} else { } else {
tcg_out_insn(s, RRF, OGRK, a0, a1, a2); tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
} }
@ -2252,8 +2246,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (const_args[2]) { if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_xori(s, TCG_TYPE_I64, a0, a2); tgen_xori(s, TCG_TYPE_I64, a0, a2);
} else if (a0 == a1) {
tcg_out_insn(s, RRE, XGR, a0, a2);
} else { } else {
tcg_out_insn(s, RRF, XGRK, a0, a1, a2); tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
} }
@ -2926,9 +2918,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64: case INDEX_op_or_i64:
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
return (HAVE_FACILITY(DISTINCT_OPS) return C_O1_I2(r, r, ri);
? C_O1_I2(r, r, ri)
: C_O1_I2(r, 0, ri));
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
return C_O1_I2(r, 0, ri); return C_O1_I2(r, 0, ri);
@ -2938,9 +2928,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
case INDEX_op_sar_i32: case INDEX_op_sar_i32:
return (HAVE_FACILITY(DISTINCT_OPS) return C_O1_I2(r, r, ri);
? C_O1_I2(r, r, ri)
: C_O1_I2(r, 0, ri));
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:

1
tcg/s390x/tcg-target.h
View File

@ -62,7 +62,6 @@ typedef enum TCGReg {
/* Facilities that are checked at runtime. */ /* Facilities that are checked at runtime. */
#define FACILITY_DISTINCT_OPS 45
#define FACILITY_LOAD_ON_COND2 53 #define FACILITY_LOAD_ON_COND2 53
#define FACILITY_VECTOR 129 #define FACILITY_VECTOR 129
#define FACILITY_VECTOR_ENH1 135 #define FACILITY_VECTOR_ENH1 135