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target/riscv: Use extracts for sraiw and srliw

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These operations can be done in one instruction on some hosts.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:18 -07:00 committed by Alistair Francis
parent 89c883091f
commit 23c1088689
1 changed files with 12 additions and 2 deletions
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14
target/riscv/insn_trans/trans_rvi.c.inc
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@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
}
static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
}
static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)