linux-user/elfload.c: Add missing arm and arm64 hwcap values
Our lists of Arm 32 and 64 bit hwcap values have lagged behind the Linux kernel. Update them to include all the bits defined as of upstream Linux git commit a48fa7efaf1161c1 (in the middle of the kernel 6.6 dev cycle). For 64-bit, we don't yet implement any of the features reported via these hwcap bits. For 32-bit we do in fact already implement them all; we'll add the code to set them in a subsequent commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -402,6 +402,12 @@ enum
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ARM_HWCAP_ARM_VFPD32 = 1 << 19,
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ARM_HWCAP_ARM_LPAE = 1 << 20,
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ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
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ARM_HWCAP_ARM_FPHP = 1 << 22,
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ARM_HWCAP_ARM_ASIMDHP = 1 << 23,
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ARM_HWCAP_ARM_ASIMDDP = 1 << 24,
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ARM_HWCAP_ARM_ASIMDFHM = 1 << 25,
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ARM_HWCAP_ARM_ASIMDBF16 = 1 << 26,
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ARM_HWCAP_ARM_I8MM = 1 << 27,
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};
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enum {
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@ -410,6 +416,8 @@ enum {
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ARM_HWCAP2_ARM_SHA1 = 1 << 2,
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ARM_HWCAP2_ARM_SHA2 = 1 << 3,
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ARM_HWCAP2_ARM_CRC32 = 1 << 4,
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ARM_HWCAP2_ARM_SB = 1 << 5,
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ARM_HWCAP2_ARM_SSBS = 1 << 6,
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};
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/* The commpage only exists for 32 bit kernels */
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@ -540,6 +548,12 @@ const char *elf_hwcap_str(uint32_t bit)
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[__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] = "vfpd32",
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[__builtin_ctz(ARM_HWCAP_ARM_LPAE )] = "lpae",
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[__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] = "evtstrm",
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[__builtin_ctz(ARM_HWCAP_ARM_FPHP )] = "fphp",
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[__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP )] = "asimdhp",
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[__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP )] = "asimddp",
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[__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] = "asimdfhm",
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[__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] = "asimdbf16",
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[__builtin_ctz(ARM_HWCAP_ARM_I8MM )] = "i8mm",
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};
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return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
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@ -553,6 +567,8 @@ const char *elf_hwcap2_str(uint32_t bit)
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[__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] = "sha1",
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[__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] = "sha2",
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[__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] = "crc32",
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[__builtin_ctz(ARM_HWCAP2_ARM_SB )] = "sb",
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[__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] = "ssbs",
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};
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return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
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@ -696,6 +712,20 @@ enum {
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ARM_HWCAP2_A64_SME_B16F32 = 1 << 28,
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ARM_HWCAP2_A64_SME_F32F32 = 1 << 29,
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ARM_HWCAP2_A64_SME_FA64 = 1 << 30,
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ARM_HWCAP2_A64_WFXT = 1ULL << 31,
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ARM_HWCAP2_A64_EBF16 = 1ULL << 32,
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ARM_HWCAP2_A64_SVE_EBF16 = 1ULL << 33,
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ARM_HWCAP2_A64_CSSC = 1ULL << 34,
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ARM_HWCAP2_A64_RPRFM = 1ULL << 35,
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ARM_HWCAP2_A64_SVE2P1 = 1ULL << 36,
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ARM_HWCAP2_A64_SME2 = 1ULL << 37,
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ARM_HWCAP2_A64_SME2P1 = 1ULL << 38,
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ARM_HWCAP2_A64_SME_I16I32 = 1ULL << 39,
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ARM_HWCAP2_A64_SME_BI32I32 = 1ULL << 40,
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ARM_HWCAP2_A64_SME_B16B16 = 1ULL << 41,
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ARM_HWCAP2_A64_SME_F16F16 = 1ULL << 42,
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ARM_HWCAP2_A64_MOPS = 1ULL << 43,
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ARM_HWCAP2_A64_HBC = 1ULL << 44,
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};
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#define ELF_HWCAP get_elf_hwcap()
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@ -851,6 +881,20 @@ const char *elf_hwcap2_str(uint32_t bit)
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[__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] = "smeb16f32",
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[__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] = "smef32f32",
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[__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] = "smefa64",
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[__builtin_ctz(ARM_HWCAP2_A64_WFXT )] = "wfxt",
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[__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] = "ebf16",
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[__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] = "sveebf16",
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[__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] = "cssc",
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[__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] = "rprfm",
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[__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] = "sve2p1",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] = "sme2",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] = "sme2p1",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] = "smei16i32",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] = "smebi32i32",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] = "smeb16b16",
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[__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] = "smef16f16",
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[__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] = "mops",
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[__builtin_ctzll(ARM_HWCAP2_A64_HBC )] = "hbc",
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};
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return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
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