hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
The SSE-300 has only one CPU and so no INITSVTOR1. It does have INITSVTOR0, but unlike the SSE-200 this register now has a LOCK bit which can be set to 1 to prevent any further writes to the register. Implement these differences. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-16-peter.maydell@linaro.org
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@ -45,6 +45,8 @@ REG32(SWRESET, 0x108)
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FIELD(SWRESET, SWRESETREQ, 9, 1)
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REG32(GRETREG, 0x10c)
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REG32(INITSVTOR0, 0x110)
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FIELD(INITSVTOR0, LOCK, 0, 1)
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FIELD(INITSVTOR0, VTOR, 7, 25)
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REG32(INITSVTOR1, 0x114)
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REG32(CPUWAIT, 0x118)
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REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
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@ -167,6 +169,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_SSE200:
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r = s->initsvtor1;
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break;
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case ARMSSE_SSE300:
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goto bad_offset;
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default:
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g_assert_not_reached();
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}
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@ -358,8 +362,25 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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s->gretreg = value;
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break;
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case A_INITSVTOR0:
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s->initsvtor0 = value;
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set_init_vtor(0, s->initsvtor0);
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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/* SSE300 has a LOCK bit which prevents further writes when set */
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if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit INITSVTOR0 write when register locked\n");
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break;
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}
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s->initsvtor0 = value;
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set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK);
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break;
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case ARMSSE_IOTKIT:
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case ARMSSE_SSE200:
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s->initsvtor0 = value;
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set_init_vtor(0, s->initsvtor0);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case A_CPUWAIT:
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switch (s->sse_version) {
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@ -464,6 +485,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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s->initsvtor1 = value;
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set_init_vtor(1, s->initsvtor1);
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break;
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case ARMSSE_SSE300:
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goto bad_offset;
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default:
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g_assert_not_reached();
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}
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