Sanitize mips exception handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -461,10 +461,10 @@ int cpu_exec(CPUState *env1)
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}
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#elif defined(TARGET_MIPS)
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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(env->CP0_Status & (1 << CP0St_IE)) &&
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(env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
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!(env->hflags & MIPS_HFLAG_EXL) &&
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!(env->hflags & MIPS_HFLAG_ERL) &&
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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/* Raise it */
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env->exception_index = EXCP_EXT_INTERRUPT;
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@ -80,6 +80,7 @@ typedef void * host_reg_t;
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typedef struct FILE FILE;
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extern int fprintf(FILE *, const char *, ...);
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extern int fputs(const char *, FILE *);
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extern int printf(const char *, ...);
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#undef NULL
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#define NULL 0
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@ -5,18 +5,17 @@
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IRQ may change */
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void cpu_mips_update_irq(CPUState *env)
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{
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if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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(env->CP0_Status & (1 << CP0St_IE)) &&
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!(env->hflags & MIPS_HFLAG_EXL) &&
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!(env->hflags & MIPS_HFLAG_ERL) &&
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if ((env->CP0_Status & (1 << CP0St_IE)) &&
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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!(env->interrupt_request & CPU_INTERRUPT_HARD)) {
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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} else {
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} else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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void cpu_mips_irq_request(void *opaque, int irq, int level)
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{
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@ -248,8 +248,6 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_TMASK 0x007F
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#define MIPS_HFLAG_MODE 0x001F /* execution modes */
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#define MIPS_HFLAG_UM 0x0001 /* user mode */
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#define MIPS_HFLAG_ERL 0x0002 /* Error mode */
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#define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
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#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
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#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
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#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
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@ -90,7 +90,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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if (user_mode && address > 0x7FFFFFFFUL)
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return TLBRET_BADADDR;
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if (address < (int32_t)0x80000000UL) {
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if (!(env->hflags & MIPS_HFLAG_ERL)) {
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if (!(env->CP0_Status & (1 << CP0St_ERL))) {
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type);
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#else
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@ -289,21 +289,18 @@ void do_interrupt (CPUState *env)
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goto set_DEPC;
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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goto set_DEPC;
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_DEPC = env->PC - 4;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_DEPC = env->PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM;
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env->hflags &= ~MIPS_HFLAG_UM;
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/* EJTAG probe trap enable is not implemented... */
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env->PC = (int32_t)0xBFC00480;
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break;
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@ -311,25 +308,22 @@ void do_interrupt (CPUState *env)
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cpu_reset(env);
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break;
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case EXCP_SRESET:
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env->CP0_Status = (1 << CP0St_SR);
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env->CP0_Status |= (1 << CP0St_SR);
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env->CP0_WatchLo = 0;
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goto set_error_EPC;
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case EXCP_NMI:
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env->CP0_Status = (1 << CP0St_NMI);
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env->CP0_Status |= (1 << CP0St_NMI);
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set_error_EPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_ErrorEPC = env->PC - 4;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_ErrorEPC = env->PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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env->hflags |= MIPS_HFLAG_ERL;
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags &= ~MIPS_HFLAG_UM;
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env->PC = (int32_t)0xBFC00000;
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break;
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case EXCP_MCHECK:
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@ -350,7 +344,7 @@ void do_interrupt (CPUState *env)
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goto set_EPC;
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case EXCP_TLBL:
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cause = 2;
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if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
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offset = 0x000;
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goto set_EPC;
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case EXCP_IBE:
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@ -384,28 +378,29 @@ void do_interrupt (CPUState *env)
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goto set_EPC;
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case EXCP_TLBS:
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cause = 3;
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if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
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offset = 0x000;
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goto set_EPC;
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set_EPC:
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_EPC = env->PC - 4;
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if (!(env->hflags & MIPS_HFLAG_EXL))
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_EPC = env->PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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} else {
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env->CP0_Status |= (1 << CP0St_EXL);
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env->hflags &= ~MIPS_HFLAG_UM;
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}
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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env->PC = (int32_t)0xBFC00200;
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} else {
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env->PC = (int32_t)0x80000000;
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}
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env->hflags |= MIPS_HFLAG_EXL;
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env->CP0_Status |= (1 << CP0St_EXL);
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env->PC += offset;
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env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
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break;
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@ -1105,12 +1105,6 @@ void op_mfc0_compare (void)
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void op_mfc0_status (void)
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{
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T0 = env->CP0_Status;
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if (env->hflags & MIPS_HFLAG_UM)
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T0 |= (1 << CP0St_UM);
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if (env->hflags & MIPS_HFLAG_ERL)
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T0 |= (1 << CP0St_ERL);
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if (env->hflags & MIPS_HFLAG_EXL)
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T0 |= (1 << CP0St_EXL);
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RETURN();
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}
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@ -1365,20 +1359,10 @@ void op_mtc0_status (void)
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{
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uint32_t val, old;
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val = (int32_t)T0 & 0xFA78FF01;
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/* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops,
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no 64bit addressing implemented. */
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val = (int32_t)T0 & 0xF878FF17;
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old = env->CP0_Status;
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if (T0 & (1 << CP0St_UM))
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env->hflags |= MIPS_HFLAG_UM;
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else
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env->hflags &= ~MIPS_HFLAG_UM;
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if (T0 & (1 << CP0St_ERL))
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env->hflags |= MIPS_HFLAG_ERL;
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else
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env->hflags &= ~MIPS_HFLAG_ERL;
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if (T0 & (1 << CP0St_EXL))
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env->hflags |= MIPS_HFLAG_EXL;
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else
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env->hflags &= ~MIPS_HFLAG_EXL;
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env->CP0_Status = val;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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CALL_FROM_TB2(do_mtc0_status_debug, old, val);
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@ -1662,6 +1646,15 @@ void op_dmtc0_errorepc (void)
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# define DEBUG_FPU_STATE() do { } while(0)
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#endif
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void op_cp0_enabled(void)
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{
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if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
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(env->hflags & MIPS_HFLAG_UM)) {
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CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 0);
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}
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RETURN();
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}
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void op_cp1_enabled(void)
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{
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if (!(env->CP0_Status & (1 << CP0St_CU1))) {
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@ -2091,15 +2084,18 @@ void debug_eret (void);
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void op_eret (void)
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{
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CALL_FROM_TB0(debug_eret);
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if (env->hflags & MIPS_HFLAG_ERL) {
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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env->PC = env->CP0_ErrorEPC;
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env->hflags &= ~MIPS_HFLAG_ERL;
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env->CP0_Status &= ~(1 << CP0St_ERL);
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} else {
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env->PC = env->CP0_EPC;
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env->hflags &= ~MIPS_HFLAG_EXL;
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env->CP0_Status &= ~(1 << CP0St_EXL);
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}
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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(env->CP0_Status & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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env->CP0_LLAddr = 1;
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RETURN();
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}
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@ -2108,6 +2104,13 @@ void op_deret (void)
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{
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CALL_FROM_TB0(debug_eret);
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env->PC = env->CP0_DEPC;
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env->hflags |= MIPS_HFLAG_DM;
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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(env->CP0_Status & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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env->CP0_LLAddr = 1;
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RETURN();
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}
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@ -509,9 +509,11 @@ void dump_sc (void)
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void debug_eret (void)
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{
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if (loglevel) {
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fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx " ErrorEPC " TARGET_FMT_lx " (%d)\n",
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env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
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env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
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fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
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env->PC, env->CP0_EPC);
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if (env->CP0_Status & (1 << CP0St_ERL))
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
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fputs("\n", logfile);
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}
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}
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@ -4022,17 +4022,6 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
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{
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const char *opn = "unk";
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if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
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(ctx->hflags & MIPS_HFLAG_UM)) &&
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!(ctx->hflags & MIPS_HFLAG_ERL) &&
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!(ctx->hflags & MIPS_HFLAG_EXL)) {
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "CP0 is not usable\n");
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}
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generate_exception (ctx, EXCP_CpU);
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return;
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}
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switch (opc) {
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case OPC_MFC0:
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if (rt == 0) {
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@ -4818,6 +4807,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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}
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break;
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case OPC_CP0:
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gen_op_cp0_enabled();
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op1 = MASK_CP0(ctx->opcode);
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switch (op1) {
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case OPC_MFC0:
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@ -5258,12 +5248,6 @@ void cpu_dump_state (CPUState *env, FILE *f,
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}
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c0_status = env->CP0_Status;
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if (env->hflags & MIPS_HFLAG_UM)
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c0_status |= (1 << CP0St_UM);
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if (env->hflags & MIPS_HFLAG_ERL)
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c0_status |= (1 << CP0St_ERL);
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if (env->hflags & MIPS_HFLAG_EXL)
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c0_status |= (1 << CP0St_EXL);
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cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
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c0_status, env->CP0_Cause, env->CP0_EPC);
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@ -5304,6 +5288,7 @@ void cpu_reset (CPUMIPSState *env)
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} else {
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env->CP0_ErrorEPC = env->PC;
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}
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env->hflags = 0;
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env->PC = (int32_t)0xBFC00000;
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#if defined (MIPS_USES_R4K_TLB)
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env->CP0_Random = MIPS_TLB_NB - 1;
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@ -5314,7 +5299,6 @@ void cpu_reset (CPUMIPSState *env)
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env->CP0_EBase = 0x80000000;
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env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
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env->CP0_WatchLo = 0;
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env->hflags = MIPS_HFLAG_ERL;
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/* Count register increments in debug mode, EJTAG version 1 */
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env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
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#endif
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