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target/mips: Introduce ase_msa_available() helper 

Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-11-29 23:22:20 +01:00
parent d7efb69382
commit 25a1362875
4 changed files with 15 additions and 11 deletions
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2
target/mips/cpu.c
View File

@ -533,7 +533,7 @@ static void mips_cpu_reset(DeviceState *dev)
}
/* MSA */
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
if (ase_msa_available(env)) {
msa_reset(env);
}

6
target/mips/cpu.h
View File

@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
/* Check presence of MSA implementation */
static inline bool ase_msa_available(CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MSAP);
}
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{

12
target/mips/kvm.c
View File

@ -79,7 +79,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
if (kvm_mips_msa_cap && ase_msa_available(env)) {
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
if (ret < 0) {
/* mark unsupported so it gets disabled on reset */
@ -105,7 +105,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu)
warn_report("KVM does not support FPU, disabling");
env->CP0_Config1 &= ~(1 << CP0C1_FP);
}
if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
if (!kvm_mips_msa_cap && ase_msa_available(env)) {
warn_report("KVM does not support MSA, disabling");
env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
}
@ -618,7 +618,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
* FPU register state is a subset of MSA vector state, so don't put FPU
* registers if we're emulating a CPU with MSA.
*/
if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@ -637,7 +637,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
}
/* Only put MSA state if we're emulating a CPU with MSA */
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
if (ase_msa_available(env)) {
/* MSA Control Registers */
if (level == KVM_PUT_FULL_STATE) {
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
@ -698,7 +698,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
* FPU register state is a subset of MSA vector state, so don't save FPU
* registers if we're emulating a CPU with MSA.
*/
if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@ -717,7 +717,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
}
/* Only get MSA state if we're emulating a CPU with MSA */
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
if (ase_msa_available(env)) {
/* MSA Control Registers */
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
&env->msair);

6
target/mips/translate.c
View File

@ -24919,8 +24919,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
@ -25022,8 +25021,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DLSA:
if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;