hw/arm/mps2-tz: Add new mps3-an524 board
Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
a113aef998
commit
25ff112a8c
149
hw/arm/mps2-tz.c
149
hw/arm/mps2-tz.c
@ -16,6 +16,7 @@
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* This source file covers the following FPGA images, for TrustZone cores:
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* "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
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* "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
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* "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
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*
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* Links to the TRM for the board itself and to the various Application
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* Notes which document the FPGA images can be found here:
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@ -27,11 +28,13 @@
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
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* Application Note AN521:
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
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* Application Note AN524:
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* https://developer.arm.com/documentation/dai0524/latest/
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*
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* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
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* (ARM ECM0601256) for the details of some of the device layout:
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines
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* Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
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* most of the device layout:
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*
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@ -65,12 +68,13 @@
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#include "hw/qdev-clock.h"
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#include "qom/object.h"
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#define MPS2TZ_NUMIRQ_MAX 92
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#define MPS2TZ_NUMIRQ_MAX 95
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#define MPS2TZ_RAM_MAX 4
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typedef enum MPS2TZFPGAType {
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FPGA_AN505,
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FPGA_AN521,
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FPGA_AN524,
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} MPS2TZFPGAType;
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/*
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@ -121,13 +125,15 @@ struct MPS2TZMachineState {
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TZPPC ppc[5];
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TZMPC mpc[3];
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PL022State spi[5];
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ArmSbconI2CState i2c[4];
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ArmSbconI2CState i2c[5];
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UnimplementedDeviceState i2s_audio;
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UnimplementedDeviceState gpio[4];
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UnimplementedDeviceState gfx;
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UnimplementedDeviceState cldc;
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UnimplementedDeviceState rtc;
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PL080State dma[4];
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TZMSC msc[4];
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CMSDKAPBUART uart[5];
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CMSDKAPBUART uart[6];
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SplitIRQ sec_resp_splitter;
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qemu_or_irq uart_irq_orgate;
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DeviceState *lan9118;
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@ -139,18 +145,38 @@ struct MPS2TZMachineState {
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#define TYPE_MPS2TZ_MACHINE "mps2tz"
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#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
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#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
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#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
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OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
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/* Slow 32Khz S32KCLK frequency in Hz */
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#define S32KCLK_FRQ (32 * 1000)
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/*
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* The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
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* emulation of that much guest RAM, so artificially make it smaller.
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*/
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#if HOST_LONG_BITS == 32
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#define MPS3_DDR_SIZE (1 * GiB)
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#else
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#define MPS3_DDR_SIZE (2 * GiB)
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#endif
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static const uint32_t an505_oscclk[] = {
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40000000,
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24580000,
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25000000,
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};
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static const uint32_t an524_oscclk[] = {
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24000000,
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32000000,
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50000000,
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50000000,
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24576000,
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23750000,
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};
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static const RAMInfo an505_raminfo[] = { {
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.name = "ssram-0",
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.base = 0x00000000,
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@ -188,6 +214,37 @@ static const RAMInfo an505_raminfo[] = { {
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},
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};
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static const RAMInfo an524_raminfo[] = { {
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.name = "bram",
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.base = 0x00000000,
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.size = 512 * KiB,
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.mpc = 0,
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.mrindex = 0,
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}, {
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.name = "sram",
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.base = 0x20000000,
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.size = 32 * 4 * KiB,
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.mpc = 1,
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.mrindex = 1,
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}, {
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/* We don't model QSPI flash yet; for now expose it as simple ROM */
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.name = "QSPI",
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.base = 0x28000000,
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.size = 8 * MiB,
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.mpc = 1,
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.mrindex = 2,
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.flags = IS_ROM,
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}, {
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.name = "DDR",
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.base = 0x60000000,
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.size = MPS3_DDR_SIZE,
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.mpc = 2,
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.mrindex = -1,
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}, {
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.name = NULL,
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},
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};
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static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
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{
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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@ -717,12 +774,66 @@ static void mps2tz_common_init(MachineState *machine)
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},
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};
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const PPCInfo an524_ppcs[] = { {
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.name = "apb_ppcexp0",
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.ports = {
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{ "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
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{ "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
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{ "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
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},
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}, {
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.name = "apb_ppcexp1",
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.ports = {
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{ "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 },
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{ "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 },
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{ "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } },
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{ "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } },
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{ "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } },
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{ "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 },
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{ "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 },
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{ /* port 7 reserved */ },
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{ "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 },
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},
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}, {
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.name = "apb_ppcexp2",
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.ports = {
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{ "scc", make_scc, &mms->scc, 0x41300000, 0x1000 },
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{ "i2s-audio", make_unimp_dev, &mms->i2s_audio,
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0x41301000, 0x1000 },
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{ "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 },
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{ "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } },
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{ "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } },
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{ "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } },
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{ "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } },
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{ "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } },
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{ "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } },
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{ /* port 9 reserved */ },
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{ "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 },
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{ "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 },
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},
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}, {
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.name = "ahb_ppcexp0",
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.ports = {
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{ "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
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{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
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{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
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{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
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{ "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } },
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},
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},
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};
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switch (mmc->fpga_type) {
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case FPGA_AN505:
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case FPGA_AN521:
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ppcs = an505_ppcs;
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num_ppcs = ARRAY_SIZE(an505_ppcs);
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break;
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case FPGA_AN524:
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ppcs = an524_ppcs;
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num_ppcs = ARRAY_SIZE(an524_ppcs);
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break;
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default:
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g_assert_not_reached();
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}
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@ -900,6 +1011,29 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
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mps2tz_set_default_ram_info(mmc);
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}
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static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
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mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
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mc->default_cpus = 2;
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mc->min_cpus = mc->default_cpus;
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mc->max_cpus = mc->default_cpus;
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mmc->fpga_type = FPGA_AN524;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
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mmc->scc_id = 0x41045240;
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mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
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mmc->oscclk = an524_oscclk;
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mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
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mmc->fpgaio_num_leds = 10;
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mmc->fpgaio_has_switches = true;
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mmc->numirq = 95;
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mmc->raminfo = an524_raminfo;
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mmc->armsse_type = TYPE_SSE200;
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mps2tz_set_default_ram_info(mmc);
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}
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static const TypeInfo mps2tz_info = {
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.name = TYPE_MPS2TZ_MACHINE,
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.parent = TYPE_MACHINE,
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@ -925,11 +1059,18 @@ static const TypeInfo mps2tz_an521_info = {
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.class_init = mps2tz_an521_class_init,
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};
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static const TypeInfo mps3tz_an524_info = {
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.name = TYPE_MPS3TZ_AN524_MACHINE,
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.parent = TYPE_MPS2TZ_MACHINE,
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.class_init = mps3tz_an524_class_init,
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};
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static void mps2tz_machine_init(void)
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{
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type_register_static(&mps2tz_info);
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type_register_static(&mps2tz_an505_info);
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type_register_static(&mps2tz_an521_info);
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type_register_static(&mps3tz_an524_info);
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}
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type_init(mps2tz_machine_init);
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