From 2607e76ffde4b0620428500a00c354c58578a933 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sat, 27 Aug 2022 00:13:40 +0200 Subject: [PATCH] target/i386: check SSE table flags instead of hardcoding opcodes Put more flags to work to avoid hardcoding lists of opcodes. The op7 case for SSE_OPF_CMP is included for homogeneity and because AVX needs it, but it is never used by SSE or MMX. Extracted from a patch by Paul Brook . Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 75 +++++++++++++++---------------------- 1 file changed, 31 insertions(+), 44 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c76f6dba11..849c40b685 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3909,7 +3909,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); op6->op[b1](cpu_env, s->ptr0, s->ptr1); - if (b == 0x17) { + if (op6->flags & SSE_OPF_CMP) { set_cc_op(s, CC_OP_EFLAGS); } break; @@ -4463,6 +4463,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); op7->op[b1](cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val)); + if (op7->flags & SSE_OPF_CMP) { + set_cc_op(s, CC_OP_EFLAGS); + } break; case 0x33a: @@ -4518,28 +4521,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, int sz = 4; gen_lea_modrm(env, s, modrm); - op2_offset = offsetof(CPUX86State,xmm_t0); + op2_offset = offsetof(CPUX86State, xmm_t0); - switch (b) { - case 0x50 ... 0x5a: - case 0x5c ... 0x5f: - case 0xc2: - /* Most sse scalar operations. */ - if (b1 == 2) { - sz = 2; - } else if (b1 == 3) { - sz = 3; - } - break; - - case 0x2e: /* ucomis[sd] */ - case 0x2f: /* comis[sd] */ - if (b1 == 0) { - sz = 2; + if (sse_op_flags & SSE_OPF_SCALAR) { + if (sse_op_flags & SSE_OPF_CMP) { + /* ucomis[sd], comis[sd] */ + if (b1 == 0) { + sz = 2; + } else { + sz = 3; + } } else { - sz = 3; + /* Most sse scalar operations. */ + if (b1 == 2) { + sz = 2; + } else if (b1 == 3) { + sz = 3; + } } - break; } switch (sz) { @@ -4585,26 +4584,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, return; } } - switch(b) { - case 0x70: /* pshufx insn */ - case 0xc6: /* pshufx insn */ + tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); + tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); + if (sse_op_flags & SSE_OPF_SHUF) { val = x86_ldub_code(env, s); - tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); - tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); /* XXX: introduce a new table? */ sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; sse_fn_ppi(s->ptr0, s->ptr1, tcg_const_i32(val)); - break; - case 0xc2: - /* compare insns, bits 7:3 (7:5 for AVX) are ignored */ - val = x86_ldub_code(env, s) & 7; - sse_fn_epp = sse_op_table4[val][b1]; - - tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); - tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); - sse_fn_epp(cpu_env, s->ptr0, s->ptr1); - break; - case 0xf7: + } else if (b == 0xf7) { /* maskmov : we must prepare A0 */ if (mod != 3) { goto illegal_op; @@ -4613,19 +4600,19 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_extu(s->aflag, s->A0); gen_add_A0_ds_seg(s); - tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); - tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); /* XXX: introduce a new table? */ sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; sse_fn_eppt(cpu_env, s->ptr0, s->ptr1, s->A0); - break; - default: - tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset); - tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset); + } else if (b == 0xc2) { + /* compare insns, bits 7:3 (7:5 for AVX) are ignored */ + val = x86_ldub_code(env, s) & 7; + sse_fn_epp = sse_op_table4[val][b1]; + sse_fn_epp(cpu_env, s->ptr0, s->ptr1); + } else { sse_fn_epp(cpu_env, s->ptr0, s->ptr1); - break; } - if (b == 0x2e || b == 0x2f) { + + if (sse_op_flags & SSE_OPF_CMP) { set_cc_op(s, CC_OP_EFLAGS); } }