target/riscv: Make riscv_cpu_tlb_fill sysemu only
The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env)
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sigcode = TARGET_TRAP_BRKPT;
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sigcode = TARGET_TRAP_BRKPT;
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sigaddr = env->pc;
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sigaddr = env->pc;
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break;
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break;
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case RISCV_EXCP_INST_PAGE_FAULT:
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case RISCV_EXCP_LOAD_PAGE_FAULT:
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case RISCV_EXCP_STORE_PAGE_FAULT:
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signum = TARGET_SIGSEGV;
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sigcode = TARGET_SEGV_MAPERR;
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sigaddr = env->badaddr;
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break;
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case RISCV_EXCP_SEMIHOST:
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case RISCV_EXCP_SEMIHOST:
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env->gpr[xA0] = do_common_semihosting(cs);
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env->gpr[xA0] = do_common_semihosting(cs);
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env->pc += 4;
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env->pc += 4;
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@ -694,9 +694,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
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static const struct TCGCPUOps riscv_tcg_ops = {
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static const struct TCGCPUOps riscv_tcg_ops = {
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.initialize = riscv_translate_init,
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.initialize = riscv_translate_init,
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.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
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.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
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.tlb_fill = riscv_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = riscv_cpu_tlb_fill,
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.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
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.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
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.do_interrupt = riscv_cpu_do_interrupt,
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.do_interrupt = riscv_cpu_do_interrupt,
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.do_transaction_failed = riscv_cpu_do_transaction_failed,
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.do_transaction_failed = riscv_cpu_do_transaction_failed,
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@ -814,7 +814,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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riscv_cpu_two_stage_lookup(mmu_idx);
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riscv_cpu_two_stage_lookup(mmu_idx);
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riscv_raise_exception(env, cs->exception_index, retaddr);
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riscv_raise_exception(env, cs->exception_index, retaddr);
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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MMUAccessType access_type, int mmu_idx,
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@ -822,7 +821,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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{
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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CPURISCVState *env = &cpu->env;
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#ifndef CONFIG_USER_ONLY
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vaddr im_address;
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vaddr im_address;
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hwaddr pa = 0;
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hwaddr pa = 0;
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int prot, prot2, prot_pmp;
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int prot, prot2, prot_pmp;
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@ -954,25 +952,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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}
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}
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return true;
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return true;
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#else
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
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break;
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case MMU_DATA_LOAD:
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cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
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break;
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default:
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g_assert_not_reached();
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}
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env->badaddr = address;
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cpu_loop_exit_restore(cs, retaddr);
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#endif
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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/*
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/*
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* Handle Traps
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* Handle Traps
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