exec: optimize remaining address_space_* cases
Do them right before the next patch generalizes them into a multi-included file. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
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d1e8e8ecc3
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2651efe7f5
126
exec.c
126
exec.c
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@ -3243,17 +3243,37 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
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return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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}
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/* XXX: optimize */
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uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
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uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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MemTxAttrs attrs, MemTxResult *result)
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{
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{
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uint8_t val;
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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MemTxResult r;
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bool release_lock = false;
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r = address_space_rw(as, addr, attrs, &val, 1, 0);
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, false);
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if (!memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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val = ldub_p(ptr);
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r = MEMTX_OK;
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}
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if (result) {
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if (result) {
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*result = r;
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*result = r;
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}
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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return val;
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return val;
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}
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}
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@ -3493,17 +3513,35 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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}
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/* XXX: optimize */
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void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
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void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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MemTxAttrs attrs, MemTxResult *result)
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{
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{
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uint8_t v = val;
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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MemTxResult r;
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bool release_lock = false;
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r = address_space_rw(as, addr, attrs, &v, 1, 1);
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, true);
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if (!memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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stb_p(ptr, val);
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invalidate_and_set_dirty(mr, addr1, 1);
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r = MEMTX_OK;
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}
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if (result) {
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if (result) {
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*result = r;
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*result = r;
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}
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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}
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}
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void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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@ -3602,37 +3640,79 @@ void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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}
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/* XXX: optimize */
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static inline void address_space_stq_internal(AddressSpace *as,
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void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
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hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result)
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MemTxAttrs attrs,
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MemTxResult *result,
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enum device_endian endian)
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{
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 8;
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hwaddr addr1;
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MemTxResult r;
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MemTxResult r;
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val = tswap64(val);
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bool release_lock = false;
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r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, true);
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if (l < 8 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap64(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap64(val);
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}
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#endif
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r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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stq_le_p(ptr, val);
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break;
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case DEVICE_BIG_ENDIAN:
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stq_be_p(ptr, val);
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break;
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default:
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stq_p(ptr, val);
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break;
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}
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invalidate_and_set_dirty(mr, addr1, 8);
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r = MEMTX_OK;
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}
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if (result) {
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if (result) {
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*result = r;
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*result = r;
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}
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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}
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void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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address_space_stq_internal(as, addr, val, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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}
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void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
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void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result)
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MemTxAttrs attrs, MemTxResult *result)
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{
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{
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MemTxResult r;
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address_space_stq_internal(as, addr, val, attrs, result,
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val = cpu_to_le64(val);
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DEVICE_LITTLE_ENDIAN);
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r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
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if (result) {
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*result = r;
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}
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}
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}
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void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
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void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result)
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MemTxAttrs attrs, MemTxResult *result)
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{
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{
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MemTxResult r;
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address_space_stq_internal(as, addr, val, attrs, result,
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val = cpu_to_be64(val);
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DEVICE_BIG_ENDIAN);
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r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
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if (result) {
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*result = r;
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}
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}
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}
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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