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ppc/pnv: add a LPC Controller model for POWER10

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Same a POWER9, only the MMIO window changes.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-12-05 19:44:54 +01:00 committed by David Gibson
parent 8b50ce8505
commit 2661f6ab2b
4 changed files with 53 additions and 12 deletions
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25
hw/ppc/pnv.c
View File

@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
}
pnv_dt_lpc(chip, fdt, 0);
pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
}
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
if (chip->ram_size) {
pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
}
pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
}
static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
error_setg(errp, "No ISA bus!");
return NULL;
Pnv10Chip *chip10 = PNV10_CHIP(chip);
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
TYPE_PNV10_PSI, &error_abort, NULL);
object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
TYPE_PNV10_LPC, &error_abort, NULL);
}
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
&PNV_PSI(&chip10->psi)->xscom_regs);
/* LPC */
object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
&error_abort);
object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
&chip10->lpc.xscom_regs);
chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
(uint64_t) PNV10_LPCM_BASE(chip));
}
static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)

30
hw/ppc/pnv_lpc.c
View File

@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
}
/* POWER9 only */
int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
uint64_t lpcm_size)
{
const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
char *name;
int offset, lpcm_offset;
uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
uint32_t opb_ranges[8] = { 0,
cpu_to_be32(lpcm_addr >> 32),
cpu_to_be32((uint32_t)lpcm_addr),
cpu_to_be32(PNV9_LPCM_SIZE / 2),
cpu_to_be32(PNV9_LPCM_SIZE / 2),
cpu_to_be32(lpcm_size / 2),
cpu_to_be32(lpcm_size / 2),
cpu_to_be32(lpcm_addr >> 32),
cpu_to_be32(PNV9_LPCM_SIZE / 2),
cpu_to_be32(PNV9_LPCM_SIZE / 2),
cpu_to_be32(lpcm_size / 2),
cpu_to_be32(lpcm_size / 2),
};
uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
cpu_to_be32((uint32_t)lpcm_addr),
cpu_to_be32(PNV9_LPCM_SIZE >> 32),
cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
cpu_to_be32(lpcm_size >> 32),
cpu_to_be32((uint32_t)lpcm_size),
};
uint32_t lpc_ranges[12] = { 0, 0,
cpu_to_be32(LPC_MEM_OPB_ADDR),
@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info = {
.class_init = pnv_lpc_power9_class_init,
};
static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "PowerNV LPC Controller POWER10";
}
static const TypeInfo pnv_lpc_power10_info = {
.name = TYPE_PNV10_LPC,
.parent = TYPE_PNV9_LPC,
.class_init = pnv_lpc_power10_class_init,
};
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void)
type_register_static(&pnv_lpc_info);
type_register_static(&pnv_lpc_power8_info);
type_register_static(&pnv_lpc_power9_info);
type_register_static(&pnv_lpc_power10_info);
}
type_init(pnv_lpc_register_types)

4
include/hw/ppc/pnv.h
View File

@ -115,6 +115,7 @@ typedef struct Pnv10Chip {
/*< public >*/
Pnv9Psi psi;
PnvLpcController lpc;
} Pnv10Chip;
typedef struct PnvChipClass {
@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV10_XSCOM_SIZE 0x0000000400000000ull
#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
#define PNV10_LPCM_SIZE 0x0000000100000000ull
#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)

6
include/hw/ppc/pnv_lpc.h
View File

@ -31,6 +31,9 @@
#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LPC)
typedef struct PnvLpcController {
DeviceState parent;
@ -97,6 +100,7 @@ typedef struct PnvLpcClass {
struct PnvChip;
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
uint64_t lpcm_addr, uint64_t lpcm_size);
#endif /* PPC_PNV_LPC_H */