target/riscv: set tval for triggered watchpoints
According to privileged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is triggered by hardware watchpoint. Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230131170955.752743-1-geomatsi@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1639,6 +1639,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
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tval = env->bins;
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break;
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case RISCV_EXCP_BREAKPOINT:
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if (cs->watchpoint_hit) {
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tval = cs->watchpoint_hit->hitaddr;
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cs->watchpoint_hit = NULL;
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}
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break;
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default:
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break;
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}
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@ -761,7 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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do_trigger_action(env, DBG_ACTION_BP);
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}
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} else {
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