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target/riscv: set tval for triggered watchpoints

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According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Sergey Matyukevich 2023-01-31 20:09:55 +03:00 committed by Alistair Francis
parent 606a2439ba
commit 26934f9a95
2 changed files with 6 additions and 1 deletions
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6
target/riscv/cpu_helper.c
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@ -1639,6 +1639,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
tval = env->bins;
break;
case RISCV_EXCP_BREAKPOINT:
if (cs->watchpoint_hit) {
tval = cs->watchpoint_hit->hitaddr;
cs->watchpoint_hit = NULL;
}
break;
default:
break;
}

1
target/riscv/debug.c
View File

@ -761,7 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) {
cs->watchpoint_hit = NULL;
do_trigger_action(env, DBG_ACTION_BP);
}
} else {