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tcg/mips: Try three insns with shift and add in tcg_out_movi

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These sequences are inexpensive to test.  Maxing out at three insns
results in the same space as a load plus the constant pool entry.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-08-06 11:18:25 -10:00
parent 1d159e64cc
commit 269e93ab76
1 changed files with 44 additions and 0 deletions
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44
tcg/mips/tcg-target.c.inc
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@ -569,6 +569,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long arg, TCGReg tbreg)
{
tcg_target_long tmp;
int sh, lo;
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
@ -591,6 +592,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
return;
}
/*
* Load bitmasks with a right-shift. This is good for things
* like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
* or similarly using LUI. For this to work, bit 31 must be set.
*/
if (arg > 0 && (int32_t)arg < 0) {
sh = clz64(arg);
if (tcg_out_movi_one(s, ret, arg << sh)) {
tcg_out_dsrl(s, ret, ret, sh);
return;
}
}
/*
* Load slightly larger constants using left-shift.
* Limit this sequence to 3 insns to avoid too much expansion.
*/
sh = ctz64(arg);
if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
tcg_out_dsll(s, ret, ret, sh);
return;
}
/*
* Load slightly larger constants using left-shift and add/or.
* Prefer addi with a negative immediate when that would produce
* a larger shift. For this to work, bits 15 and 16 must be set.
*/
lo = arg & 0xffff;
if (lo) {
if ((arg & 0x18000) == 0x18000) {
lo = (int16_t)arg;
}
tmp = arg - lo;
sh = ctz64(tmp);
tmp >>= sh;
if (tcg_out_movi_one(s, ret, tmp)) {
tcg_out_dsll(s, ret, ret, sh);
tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
return;
}
}
/* Otherwise, put 64-bit constants into the constant pool. */
tcg_out_movi_pool(s, ret, arg, tbreg);
}