ppc: Create cpu_ppc_set_papr() helper
And move the code adjusting the MSR mask and calling kvmppc_set_papr() to it. This allows us to add a few more things such as disabling setting of MSR:HV and appropriate LPCR bits which will be used when fixing the exception model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: removed LPCR setting ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1613,15 +1613,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, TIMEBASE_FREQ);
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/* PAPR always has exception vectors in RAM not ROM. To ensure this,
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* MSR[IP] should never be set.
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*/
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env->msr_mask &= ~(1 << 6);
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/* Tell KVM that we're in PAPR mode */
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if (kvm_enabled()) {
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kvmppc_set_papr(cpu);
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}
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu);
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if (cpu->max_compat) {
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Error *local_err = NULL;
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@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
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void store_booke_tsr (CPUPPCState *env, target_ulong val);
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void ppc_tlb_invalidate_all (CPUPPCState *env);
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void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
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void cpu_ppc_set_papr(PowerPCCPU *cpu);
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#endif
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#endif
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@ -8380,8 +8380,29 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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pcc->l1_icache_size = 0x8000;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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}
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#endif /* defined (TARGET_PPC64) */
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#if !defined(CONFIG_USER_ONLY)
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void cpu_ppc_set_papr(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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/* PAPR always has exception vectors in RAM not ROM. To ensure this,
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* MSR[IP] should never be set.
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*
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* We also disallow setting of MSR_HV
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*/
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env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
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/* Tell KVM that we're in PAPR mode */
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if (kvm_enabled()) {
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kvmppc_set_papr(cpu);
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}
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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#endif /* defined (TARGET_PPC64) */
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/*****************************************************************************/
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/* Generic CPU instantiation routine */
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