target-ppc: Add xsmaxcdp and xsmincdp instructions
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision xsmincdp: VSX Scalar Minimum Type-C Double-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2679,6 +2679,44 @@ VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
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VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
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VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
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#define VSX_MAX_MINC(name, max) \
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void helper_##name(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xa, xb; \
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bool vxsnan_flag = false, vex_flag = false; \
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\
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getVSR(rA(opcode) + 32, &xa, env); \
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getVSR(rB(opcode) + 32, &xb, env); \
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getVSR(rD(opcode) + 32, &xt, env); \
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\
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if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
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float64_is_any_nan(xb.VsrD(0)))) { \
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if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
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float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
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vxsnan_flag = true; \
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} \
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xt.VsrD(0) = xb.VsrD(0); \
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} else if ((max && \
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!float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
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(!max && \
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float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
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xt.VsrD(0) = xa.VsrD(0); \
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} else { \
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xt.VsrD(0) = xb.VsrD(0); \
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} \
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\
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vex_flag = fpscr_ve & vxsnan_flag; \
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if (vxsnan_flag) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
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} \
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if (!vex_flag) { \
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putVSR(rD(opcode) + 32, &xt, env); \
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} \
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} \
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VSX_MAX_MINC(xsmaxcdp, 1);
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VSX_MAX_MINC(xsmincdp, 0);
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/* VSX_CMP - VSX floating point compare
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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@ -431,6 +431,8 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
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DEF_HELPER_2(xscmpuqp, void, env, i32)
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DEF_HELPER_2(xsmaxdp, void, env, i32)
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DEF_HELPER_2(xsmindp, void, env, i32)
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DEF_HELPER_2(xsmaxcdp, void, env, i32)
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DEF_HELPER_2(xsmincdp, void, env, i32)
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DEF_HELPER_2(xscvdphp, void, env, i32)
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DEF_HELPER_2(xscvdpqp, void, env, i32)
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DEF_HELPER_2(xscvdpsp, void, env, i32)
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@ -808,6 +808,8 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
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GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
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GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
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@ -200,6 +200,8 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
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GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
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GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
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GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
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GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
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GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
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GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
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GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
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GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
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