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accel/tcg: Fix NB_MMU_MODES to 16 

Balance of the target/ patchset which eliminates tcg_temp_free
 Balance of the target/ patchset which eliminates tcg_const
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Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
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* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
  tcg: Drop tcg_const_*
  tcg: Drop tcg_const_*_vec
  target/tricore: Use min/max for saturate
  target/ppc: Avoid tcg_const_* in translate.c
  target/ppc: Fix gen_tlbsx_booke206
  target/ppc: Rewrite trans_ADDG6S
  target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
  target/ppc: Avoid tcg_const_* in fp-impl.c.inc
  target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
  target/ppc: Avoid tcg_const_* in xxeval
  target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
  target/ppc: Avoid tcg_const_i64 in do_vcntmb
  target/m68k: Use tcg_constant_i32 in gen_ea_mode
  target/arm: Avoid tcg_const_ptr in handle_rev
  target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
  target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
  target/arm: Avoid tcg_const_* in translate-mve.c
  target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
  target/arm: Improve trans_BFCI
  target/arm: Create gen_set_rmode, gen_restore_rmode
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-03-14 10:09:15 +00:00
parent 5cfda4ce79 0c8b6b9a63
commit 27a03171d0
67 changed files with 1166 additions and 2388 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
accel/tcg/plugin-gen.c
View File

@ -44,6 +44,7 @@
*/
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"

9
include/exec/cpu-defs.h
View File

@ -36,9 +36,6 @@
#ifndef TARGET_LONG_BITS
# error TARGET_LONG_BITS must be defined in cpu-param.h
#endif
#ifndef NB_MMU_MODES
# error NB_MMU_MODES must be defined in cpu-param.h
#endif
#ifndef TARGET_PHYS_ADDR_SPACE_BITS
# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
#endif
@ -57,6 +54,12 @@
#include "exec/target_long.h"
/*
* Fix the number of mmu modes to 16, which is also the maximum
* supported by the softmmu tlb api.
*/
#define NB_MMU_MODES 16
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* use a fully associative victim tlb of 8 entries */

4
include/tcg/tcg-op.h
View File

@ -1089,9 +1089,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
#define tcg_constant_tl tcg_constant_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
@ -1205,9 +1203,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
#define tcg_constant_tl tcg_constant_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
#define tcg_gen_sub2_tl tcg_gen_sub2_i32

83
include/tcg/tcg-temp-internal.h Normal file
View File

@ -0,0 +1,83 @@
/*
* TCG internals related to TCG temp allocation
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef TCG_TEMP_INTERNAL_H
#define TCG_TEMP_INTERNAL_H
/*
* Allocation and freeing of EBB temps is reserved to TCG internals
*/
void tcg_temp_free_internal(TCGTemp *);
static inline void tcg_temp_free_i32(TCGv_i32 arg)
{
tcg_temp_free_internal(tcgv_i32_temp(arg));
}
static inline void tcg_temp_free_i64(TCGv_i64 arg)
{
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
static inline void tcg_temp_free_i128(TCGv_i128 arg)
{
tcg_temp_free_internal(tcgv_i128_temp(arg));
}
static inline void tcg_temp_free_ptr(TCGv_ptr arg)
{
tcg_temp_free_internal(tcgv_ptr_temp(arg));
}
static inline void tcg_temp_free_vec(TCGv_vec arg)
{
tcg_temp_free_internal(tcgv_vec_temp(arg));
}
static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
return temp_tcgv_i32(t);
}
static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
return temp_tcgv_i64(t);
}
static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
return temp_tcgv_i128(t);
}
static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
return temp_tcgv_ptr(t);
}
#endif /* TCG_TEMP_FREE_H */

64
include/tcg/tcg.h
View File

@ -862,35 +862,9 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind);
void tcg_temp_free_internal(TCGTemp *);
TCGv_vec tcg_temp_new_vec(TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
static inline void tcg_temp_free_i32(TCGv_i32 arg)
{
tcg_temp_free_internal(tcgv_i32_temp(arg));
}
static inline void tcg_temp_free_i64(TCGv_i64 arg)
{
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
static inline void tcg_temp_free_i128(TCGv_i128 arg)
{
tcg_temp_free_internal(tcgv_i128_temp(arg));
}
static inline void tcg_temp_free_ptr(TCGv_ptr arg)
{
tcg_temp_free_internal(tcgv_ptr_temp(arg));
}
static inline void tcg_temp_free_vec(TCGv_vec arg)
{
tcg_temp_free_internal(tcgv_vec_temp(arg));
}
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
@ -898,13 +872,6 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i32(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
return temp_tcgv_i32(t);
}
static inline TCGv_i32 tcg_temp_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB);
@ -918,26 +885,12 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i64(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
return temp_tcgv_i64(t);
}
static inline TCGv_i64 tcg_temp_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB);
return temp_tcgv_i64(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
return temp_tcgv_i128(t);
}
static inline TCGv_i128 tcg_temp_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB);
@ -951,13 +904,6 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_ptr(t);
}
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
return temp_tcgv_ptr(t);
}
static inline TCGv_ptr tcg_temp_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB);
@ -1050,14 +996,6 @@ void tcg_remove_ops_after(TCGOp *op);
void tcg_optimize(TCGContext *s);
/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_vec tcg_const_zeros_vec(TCGType);
TCGv_vec tcg_const_ones_vec(TCGType);
TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
/*
* Locate or create a read-only temporary that is a constant.
* This kind of temporary need not be freed, but for convenience
@ -1079,10 +1017,8 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
#if UINTPTR_MAX == UINT32_MAX
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
#else
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
#endif

2
target/alpha/cpu-param.h
View File

@ -15,6 +15,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 44
#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#define NB_MMU_MODES 3
#endif

2
target/arm/cpu-param.h
View File

@ -45,6 +45,4 @@
bool guarded;
#endif
#define NB_MMU_MODES 12
#endif

12
target/arm/internals.h
View File

@ -193,16 +193,22 @@ void arm_restore_state_to_opc(CPUState *cs,
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
enum arm_fprounding {
typedef enum ARMFPRounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
FPROUNDING_NEGINF,
FPROUNDING_ZERO,
FPROUNDING_TIEAWAY,
FPROUNDING_ODD
};
} ARMFPRounding;
int arm_rmode_to_sf(int rmode);
extern const FloatRoundMode arm_rmode_to_sf_map[6];
static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
{
assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
return arm_rmode_to_sf_map[rmode];
}
static inline void aarch64_save_sp(CPUARMState *env, int el)
{

168
target/arm/tcg/translate-a64.c
View File

@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
{
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
TCGv_i32 tcg_rmode;
fpst = fpstatus_ptr(FPST_FPCR_F16);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(opcode & 7, fpst);
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
break;
}
case 0xe: /* FRINTX */
@ -6202,7 +6201,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
rmode = arm_rmode_to_sf(opcode & 7);
rmode = opcode & 7;
gen_fpst = gen_helper_rints;
break;
case 0xe: /* FRINTX */
@ -6212,14 +6211,14 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rints;
break;
case 0x10: /* FRINT32Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_s;
break;
case 0x12: /* FRINT64Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_s;
break;
case 0x13: /* FRINT64X */
@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@ -6275,7 +6273,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
rmode = arm_rmode_to_sf(opcode & 7);
rmode = opcode & 7;
gen_fpst = gen_helper_rintd;
break;
case 0xe: /* FRINTX */
@ -6285,14 +6283,14 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rintd;
break;
case 0x10: /* FRINT32Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_d;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_d;
break;
case 0x12: /* FRINT64Z */
rmode = float_round_to_zero;
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_d;
break;
case 0x13: /* FRINT64X */
@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
rmode = FPROUNDING_TIEAWAY;
}
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
switch (type) {
case 1: /* float64 */
@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
g_assert_not_reached();
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@ -7447,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
int esize = 8 << size;
int i, ofs;
int i;
int datasize = is_q ? 128 : 64;
int elements = datasize / esize;
TCGv_i64 tcg_res, tcg_resl, tcg_resh;
TCGv_i64 tcg_res[2], tcg_ele;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@ -7461,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
tcg_resl = tcg_const_i64(0);
tcg_resh = is_q ? tcg_const_i64(0) : NULL;
tcg_res = tcg_temp_new_i64();
tcg_res[0] = tcg_temp_new_i64();
tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL;
tcg_ele = tcg_temp_new_i64();
for (i = 0; i < elements; i++) {
int o, w;
switch (opcode) {
case 1: /* UZP1/2 */
{
int midpoint = elements / 2;
if (i < midpoint) {
read_vec_element(s, tcg_res, rn, 2 * i + part, size);
read_vec_element(s, tcg_ele, rn, 2 * i + part, size);
} else {
read_vec_element(s, tcg_res, rm,
read_vec_element(s, tcg_ele, rm,
2 * (i - midpoint) + part, size);
}
break;
}
case 2: /* TRN1/2 */
if (i & 1) {
read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size);
} else {
read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size);
}
break;
case 3: /* ZIP1/2 */
{
int base = part * elements / 2;
if (i & 1) {
read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
read_vec_element(s, tcg_ele, rm, base + (i >> 1), size);
} else {
read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
read_vec_element(s, tcg_ele, rn, base + (i >> 1), size);
}
break;
}
@ -7499,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
ofs = i * esize;
if (ofs < 64) {
tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
w = (i * esize) / 64;
o = (i * esize) % 64;
if (o == 0) {
tcg_gen_mov_i64(tcg_res[w], tcg_ele);
} else {
tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
tcg_gen_shli_i64(tcg_ele, tcg_ele, o);
tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele);
}
}
write_vec_element(s, tcg_resl, rd, 0, MO_64);
if (is_q) {
write_vec_element(s, tcg_resh, rd, 1, MO_64);
for (i = 0; i <= is_q; ++i) {
write_vec_element(s, tcg_res[i], rd, i, MO_64);
}
clear_vec_high(s, is_q, rd);
}
@ -8463,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
tcg_rn = tcg_temp_new_i64();
tcg_rd = tcg_temp_new_i64();
tcg_rd_narrowed = tcg_temp_new_i32();
tcg_final = tcg_const_i64(0);
tcg_final = tcg_temp_new_i64();
if (round) {
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
@ -8477,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
false, is_u_shift, size+1, shift);
narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
if (i == 0) {
tcg_gen_mov_i64(tcg_final, tcg_rd);
} else {
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
}
}
if (!is_q) {
@ -8771,9 +8771,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
assert(!(is_scalar && is_q));
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_constant_i32(fracbits);
@ -8831,7 +8830,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
/* AdvSIMD scalar shift by immediate
@ -10219,12 +10218,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
tcg_fpstatus = NULL;
tcg_rmode = NULL;
}
if (size == 3) {
@ -10276,7 +10274,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@ -12005,22 +12003,26 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
int esize = 8 << size;
int elements = dsize / esize;
TCGv_i64 tcg_rn = tcg_temp_new_i64();
TCGv_i64 tcg_rd = tcg_const_i64(0);
TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
TCGv_i64 tcg_rd[2];
for (i = 0; i < 2; i++) {
tcg_rd[i] = tcg_temp_new_i64();
tcg_gen_movi_i64(tcg_rd[i], 0);
}
for (i = 0; i < elements; i++) {
int e_rev = (i & 0xf) ^ revmask;
int off = e_rev * esize;
int w = (e_rev * esize) / 64;
int o = (e_rev * esize) % 64;
read_vec_element(s, tcg_rn, rn, i, size);
if (off >= 64) {
tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
tcg_rn, off - 64, esize);
} else {
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
}
tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
}
write_vec_element(s, tcg_rd, rd, 0, MO_64);
write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
for (i = 0; i < 2; i++) {
write_vec_element(s, tcg_rd[i], rd, i, MO_64);
}
clear_vec_high(s, true, rd);
}
}
@ -12133,7 +12135,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool need_fpstatus = false;
bool need_rmode = false;
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
@ -12283,7 +12284,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
need_fpstatus = true;
need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
if (size == 3 && !is_q) {
unallocated_encoding(s);
@ -12293,7 +12293,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
need_fpstatus = true;
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
if (size == 3 && !is_q) {
unallocated_encoding(s);
@ -12352,7 +12351,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
@ -12364,7 +12362,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x58: /* FRINTA */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
need_fpstatus = true;
if (size == 3 && !is_q) {
@ -12380,7 +12377,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
case 0x1e: /* FRINT32Z */
case 0x1f: /* FRINT64Z */
need_rmode = true;
rmode = FPROUNDING_ZERO;
/* fall through */
case 0x5e: /* FRINT32X */
@ -12406,14 +12402,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
if (need_fpstatus || need_rmode) {
if (need_fpstatus || rmode >= 0) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
} else {
tcg_fpstatus = NULL;
}
if (need_rmode) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
@ -12595,8 +12590,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
clear_vec_high(s, is_q, rd);
if (need_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (tcg_rmode) {
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@ -12625,9 +12620,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
int pass;
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
bool need_rmode = false;
bool need_fpst = true;
int rmode;
int rmode = -1;
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
@ -12676,27 +12670,22 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3f: /* FRECPX */
break;
case 0x18: /* FRINTN */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x19: /* FRINTM */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x38: /* FRINTP */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_POSINF;
break;
case 0x39: /* FRINTZ */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_ZERO;
break;
case 0x58: /* FRINTA */
need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEAWAY;
break;
@ -12706,43 +12695,33 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
/* current rounding mode */
break;
case 0x1a: /* FCVTNS */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x1b: /* FCVTMS */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x1c: /* FCVTAS */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x3a: /* FCVTPS */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x3b: /* FCVTZS */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x5a: /* FCVTNU */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x5b: /* FCVTMU */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x5c: /* FCVTAU */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x7a: /* FCVTPU */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x7b: /* FCVTZU */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x2f: /* FABS */
@ -12775,13 +12754,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
return;
}
if (need_rmode || need_fpst) {
if (rmode >= 0 || need_fpst) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16);
}
if (need_rmode) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
}
if (is_scalar) {
@ -12881,7 +12859,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (tcg_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}

56
target/arm/tcg/translate-mve.c
View File

@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
enum arm_fprounding rmode, bool u)
ARMFPRounding rmode, bool u)
{
/*
* Handle VCVT fp to int with specified rounding mode.
@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s) ||
@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current rda value, not 0.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}
fn(rda, cpu_env, qn, qm, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
!mve_check_qreg_bank(s, a->qn) ||
@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
* beat must start with the current rda value, not 0.
*/
if (a->a || mve_skip_first_beat(s)) {
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}
fn(rda, cpu_env, qn, qm, rda);
store_reg(s, a->rda, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
{ NULL, NULL }
};
TCGv_ptr qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
a->size == 3) {
@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
*/
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from Rda */
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}
qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda, cpu_env, qm, rda);
store_reg(s, a->rda, rda);
fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* No need to check Qm's bank: it is only 3 bits in decode.
*/
TCGv_ptr qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s)) {
@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current value of RdaHi:RdaLo, not zero.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from RdaHi:RdaLo */
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}
qm = mve_qreg_ptr(a->qm);
if (a->u) {
gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
} else {
gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);

28
target/arm/tcg/translate-sve.c
View File

@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
int mode, gen_helper_gvec_3_ptr *fn)
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
{
unsigned vsz;
TCGv_i32 tmode;
@ -4096,30 +4096,28 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
tmode = tcg_const_i32(mode);
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tmode, tmode, status);
tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
gen_helper_set_rmode(tmode, tmode, status);
gen_restore_rmode(tmode, status);
return true;
}
TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
float_round_nearest_even, frint_fns[a->esz])
FPROUNDING_TIEEVEN, frint_fns[a->esz])
TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
float_round_up, frint_fns[a->esz])
FPROUNDING_POSINF, frint_fns[a->esz])
TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
float_round_down, frint_fns[a->esz])
FPROUNDING_NEGINF, frint_fns[a->esz])
TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
float_round_to_zero, frint_fns[a->esz])
FPROUNDING_ZERO, frint_fns[a->esz])
TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
float_round_ties_away, frint_fns[a->esz])
FPROUNDING_TIEAWAY, frint_fns[a->esz])
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
NULL, gen_helper_sve_frecpx_h,
@ -4208,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();
tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@ -4286,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();
tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve_fcvt_ds)
FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)
static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,

26
target/arm/tcg/translate-vfp.c
View File

@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_op;
@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
tcg_shift = tcg_constant_i32(0);
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}

14
target/arm/tcg/translate.c
View File

@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
tmp = tcg_const_i32(0);
t_in = tcg_constant_i32(0);
} else {
/* BFI */
tmp = load_reg(s, a->rn);
t_in = load_reg(s, a->rn);
}
if (width != 32) {
TCGv_i32 tmp2 = load_reg(s, a->rd);
tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
}
store_reg(s, a->rd, tmp);
t_rd = load_reg(s, a->rd);
tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
store_reg(s, a->rd, t_rd);
return true;
}

17
target/arm/tcg/translate.h
View File

@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}
/*
* Set and reset rounding mode around another operation.
*/
static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
{
TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
TCGv_i32 old = tcg_temp_new_i32();
gen_helper_set_rmode(old, new, fpst);
return old;
}
static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
{
gen_helper_set_rmode(old, old, fpst);
}
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.

35
target/arm/vfp_helper.c
View File

@ -1104,33 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
}
/* Convert ARM rounding mode to softfloat */
int arm_rmode_to_sf(int rmode)
{
switch (rmode) {
case FPROUNDING_TIEAWAY:
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
/* FIXME: add support for TIEAWAY and ODD */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
rmode);
/* fall through for now */
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
break;
case FPROUNDING_POSINF:
rmode = float_round_up;
break;
case FPROUNDING_NEGINF:
rmode = float_round_down;
break;
case FPROUNDING_ZERO:
rmode = float_round_to_zero;
break;
}
return rmode;
}
const FloatRoundMode arm_rmode_to_sf_map[] = {
[FPROUNDING_TIEEVEN] = float_round_nearest_even,
[FPROUNDING_POSINF] = float_round_up,
[FPROUNDING_NEGINF] = float_round_down,
[FPROUNDING_ZERO] = float_round_to_zero,
[FPROUNDING_TIEAWAY] = float_round_ties_away,
[FPROUNDING_ODD] = float_round_to_odd,
};
/*
* Implement float64 to int32_t conversion without saturation;

1
target/avr/cpu-param.h
View File

@ -31,6 +31,5 @@
#define TARGET_PAGE_BITS 8
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
#define NB_MMU_MODES 2
#endif

48
target/avr/translate.c
View File

@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a)
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv t0 = tcg_const_i32(0);
TCGv t0 = tcg_constant_i32(0);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx)
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x0000ff));
TCGv t0 = tcg_constant_i32(ret & 0x0000ff);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x00ffff));
TCGv t0 = tcg_constant_i32(ret & 0x00ffff);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo = tcg_const_i32((ret & 0x0000ff));
TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
TCGv lo = tcg_constant_i32(ret & 0x0000ff);
TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);
tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
TCGv Rr = tcg_const_i32(Imm);
TCGv Rr = tcg_constant_i32(Imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
@ -1288,12 +1288,13 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
*/
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;
return true;
}
@ -1305,12 +1306,13 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
*/
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;
return true;
}
@ -2122,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
static bool trans_IN(DisasContext *ctx, arg_IN *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port);
return true;
@ -2135,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd);
return true;
@ -2403,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
@ -2418,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));

1
target/cris/cpu-param.h
View File

@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 2
#endif

46
target/cris/translate.c
View File

@ -175,10 +175,7 @@ static const int preg_sizes[] = {
#define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
do { \
TCGv tc = tcg_const_tl(c); \
t_gen_mov_env_TN(member, tc); \
} while (0)
t_gen_mov_env_TN(member, tcg_constant_tl(c))
static inline void t_gen_mov_TN_preg(TCGv tn, int r)
{
@ -268,8 +265,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
gen_helper_raise_exception(cpu_env, tmp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
@ -277,7 +273,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
TCGv t0, t_31;
t0 = tcg_temp_new();
t_31 = tcg_const_tl(31);
t_31 = tcg_constant_tl(31);
tcg_gen_shl_tl(d, a, b);
tcg_gen_sub_tl(t0, t_31, b);
@ -1250,7 +1246,7 @@ static int dec_addq(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@ -1274,7 +1270,7 @@ static int dec_subq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_SUB,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@ -1289,7 +1285,7 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@ -1304,7 +1300,7 @@ static int dec_andq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_AND,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@ -1318,7 +1314,7 @@ static int dec_orq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
@ -1330,7 +1326,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
@ -1945,8 +1941,8 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1);
return 2;
@ -1955,8 +1951,8 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2);
return 2;
@ -2237,7 +2233,7 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], t[1], c, memsize_zz(dc));
do_postinc(dc, memsize);
@ -2582,7 +2578,7 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
if (dc->op2 > 15) {
abort();
}
c = tcg_const_tl(dc->pc + 4);
c = tcg_constant_tl(dc->pc + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
@ -2598,7 +2594,7 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@ -2616,7 +2612,7 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8 + 4);
c = tcg_constant_tl(dc->pc + 8 + 4);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@ -2632,7 +2628,7 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
c = tcg_const_tl(dc->pc + 4 + 4);
c = tcg_constant_tl(dc->pc + 4 + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
return 2;
@ -2664,7 +2660,7 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@ -2681,7 +2677,7 @@ static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 12);
c = tcg_constant_tl(dc->pc + 12);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);
@ -2695,7 +2691,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);

26
target/cris/translate_v10.c.inc
View File

@ -251,7 +251,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -259,7 +259,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -267,7 +267,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -275,7 +275,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
op = imm & (1 << 5);
imm &= 0x1f;
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
if (op) {
cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
@ -305,7 +305,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
}
imm &= 0x1f;
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, op, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -313,7 +313,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -321,7 +321,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
@ -1014,7 +1014,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
cris_alu_m_alloc_temps(t);
insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], c, size);
break;
@ -1111,7 +1111,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
dc->jmp_pc = imm;
cris_prepare_jmp(dc, JMP_DIRECT);
@ -1121,7 +1121,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("break %d\n", dc->src);
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc + 2);
c = tcg_const_tl(dc->src + 2);
c = tcg_constant_tl(dc->src + 2);
t_gen_mov_env_TN(trap_vector, c);
t_gen_raise_exception(EXCP_BREAK);
dc->base.is_jmp = DISAS_NORETURN;
@ -1130,7 +1130,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
dc->opcode, dc->src, dc->dst);
t[0] = tcg_temp_new();
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
crisv10_prepare_memaddr(dc, t[0], size);
gen_load(dc, env_btarget, t[0], 4, 0);
@ -1153,7 +1153,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->dst, dc->src);
tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */

2
target/hexagon/cpu-param.h
View File

@ -24,6 +24,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 1
#endif

1
target/hppa/cpu-param.h
View File

@ -29,6 +29,5 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5
#endif

35
target/hppa/translate.c
View File

@ -135,8 +135,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_gen_extract2_reg tcg_gen_extract2_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
#define tcg_gen_movcond_reg tcg_gen_movcond_i64
#define tcg_gen_add2_reg tcg_gen_add2_i64
@ -228,8 +226,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_gen_extract2_reg tcg_gen_extract2_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
#define tcg_gen_movcond_reg tcg_gen_movcond_i32
#define tcg_gen_add2_reg tcg_gen_add2_i32
@ -574,7 +570,9 @@ static TCGv_i32 load_frw_i32(unsigned rt)
static TCGv_i32 load_frw0_i32(unsigned rt)
{
if (rt == 0) {
return tcg_const_i32(0);
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_movi_i32(ret, 0);
return ret;
} else {
return load_frw_i32(rt);
}
@ -582,15 +580,15 @@ static TCGv_i32 load_frw0_i32(unsigned rt)
static TCGv_i64 load_frw0_i64(unsigned rt)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (rt == 0) {
return tcg_const_i64(0);
tcg_gen_movi_i64(ret, 0);
} else {
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld32u_i64(ret, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
return ret;
}
return ret;
}
static void save_frw_i32(unsigned rt, TCGv_i32 val)
@ -613,7 +611,9 @@ static TCGv_i64 load_frd(unsigned rt)
static TCGv_i64 load_frd0(unsigned rt)
{
if (rt == 0) {
return tcg_const_i64(0);
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_movi_i64(ret, 0);
return ret;
} else {
return load_frd(rt);
}
@ -3330,7 +3330,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);
mask = tcg_const_reg(msb + (msb - 1));
mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1));
tcg_gen_and_reg(tmp, val, mask);
if (rs) {
tcg_gen_shl_reg(mask, mask, shift);
@ -3547,12 +3548,16 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
{
uint64_t ret;
if (TARGET_REGISTER_BITS == 64) {
ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */
} else {
ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */
}
nullify_over(ctx);
#if TARGET_REGISTER_BITS == 64
save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */
#else
save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */
#endif
save_frd(0, tcg_constant_i64(ret));
return nullify_end(ctx);
}

1
target/i386/cpu-param.h
View File

@ -23,6 +23,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5
#endif

83
target/i386/tcg/translate.c
View File

@ -884,7 +884,7 @@ static void gen_compute_eflags(DisasContext *s)
live = cc_op_live[s->cc_op] & ~USES_CC_SRCT;
dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2);
if (dead) {
zero = tcg_const_tl(0);
zero = tcg_constant_tl(0);
if (dead & USES_CC_DST) {
dst = zero;
}
@ -1412,7 +1412,7 @@ static void gen_helper_fp_arith_ST0_FT0(int op)
/* NOTE the exception in "r" op ordering */
static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
{
TCGv_i32 tmp = tcg_const_i32(opreg);
TCGv_i32 tmp = tcg_constant_i32(opreg);
switch (op) {
case 0:
gen_helper_fadd_STN_ST0(cpu_env, tmp);
@ -1439,7 +1439,7 @@ static void gen_exception(DisasContext *s, int trapno)
{
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno));
s->base.is_jmp = DISAS_NORETURN;
}
@ -1633,7 +1633,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
/* Store the results into the CC variables. If we know that the
variable must be dead, store unconditionally. Otherwise we'll
need to not disrupt the current contents. */
z_tl = tcg_const_tl(0);
z_tl = tcg_constant_tl(0);
if (cc_op_live[s->cc_op] & USES_CC_DST) {
tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl,
result, cpu_cc_dst);
@ -1657,7 +1657,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
}
/* Conditionally store the CC_OP value. */
z32 = tcg_const_i32(0);
z32 = tcg_constant_i32(0);
s32 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(s32, count);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
@ -1813,7 +1813,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
exactly as we computed above. */
t0 = tcg_const_i32(0);
t0 = tcg_constant_i32(0);
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, s->T1);
tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX);
@ -2497,7 +2497,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
cc.reg = t0;
}
if (!cc.use_reg2) {
cc.reg2 = tcg_const_tl(cc.imm);
cc.reg2 = tcg_constant_tl(cc.imm);
}
tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
@ -2525,7 +2525,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg)
{
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32);
gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware
@ -4344,7 +4344,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) {
TCGv imm = tcg_const_tl(x86_ldub_code(env, s));
TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
@ -4503,7 +4503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0c: /* fldenv mem */
gen_helper_fldenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
@ -4514,7 +4514,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0e: /* fnstenv mem */
gen_helper_fstenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
@ -4532,12 +4532,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x2c: /* frstor mem */
gen_helper_frstor(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
gen_helper_fsave(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
@ -4587,12 +4587,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x08: /* fld sti */
gen_helper_fpush(cpu_env);
gen_helper_fmov_ST0_STN(cpu_env,
tcg_const_i32((opreg + 1) & 7));
tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
@ -4732,27 +4732,27 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
} else {
gen_helper_fmov_FT0_STN(cpu_env,
tcg_const_i32(opreg));
tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@ -4786,7 +4786,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
@ -4795,36 +4795,36 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x2c: /* fucom st(i) */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
break;
case 0x2d: /* fucomp st(i) */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@ -4834,7 +4834,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
break;
case 0x38: /* ffreep sti, undocumented op */
gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x3c: /* df/4 */
@ -4853,7 +4853,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@ -4863,7 +4863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@ -4886,7 +4886,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
gen_helper_fmov_ST0_STN(cpu_env,
tcg_constant_i32(opreg));
gen_set_label(l1);
}
break;
@ -5092,8 +5093,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(val));
gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1),
tcg_constant_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
@ -5120,7 +5121,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!check_vm86_iopl(s)) {
break;
}
gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1));
} else {
gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
@ -5509,7 +5510,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
gen_helper_aam(cpu_env, tcg_const_i32(val));
gen_helper_aam(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
@ -5517,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
gen_helper_aad(cpu_env, tcg_const_i32(val));
gen_helper_aad(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
@ -5698,7 +5699,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
@ -5717,7 +5718,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
@ -5923,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
@ -5947,7 +5948,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
@ -5959,7 +5960,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */

1
target/loongarch/cpu-param.h
View File

@ -13,6 +13,5 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 48
#define TARGET_PAGE_BITS 14
#define NB_MMU_MODES 5
#endif

1
target/m68k/cpu-param.h
View File

@ -17,6 +17,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 2
#endif

231
target/m68k/translate.c
View File

@ -264,10 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
static void gen_raise_exception(int nr)
{
TCGv_i32 tmp;
tmp = tcg_const_i32(nr);
gen_helper_raise_exception(cpu_env, tmp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr));
}
static void gen_raise_exception_format2(DisasContext *s, int nr,
@ -471,7 +468,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
if ((ext & 0x80) == 0) {
/* base not suppressed */
if (IS_NULL_QREG(base)) {
base = tcg_const_i32(offset + bd);
base = tcg_constant_i32(offset + bd);
bd = 0;
}
if (!IS_NULL_QREG(add)) {
@ -487,7 +484,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
add = tmp;
}
} else {
add = tcg_const_i32(bd);
add = tcg_constant_i32(bd);
}
if ((ext & 3) != 0) {
/* memory indirect */
@ -623,8 +620,7 @@ static void gen_flush_flags(DisasContext *s)
break;
default:
t0 = tcg_const_i32(s->cc_op);
gen_helper_flush_flags(cpu_env, t0);
gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op));
s->cc_op_synced = 1;
break;
}
@ -785,14 +781,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
switch (reg0) {
case 0: /* Absolute short. */
offset = (int16_t)read_im16(env, s);
return tcg_const_i32(offset);
return tcg_constant_i32(offset);
case 1: /* Absolute long. */
offset = read_im32(env, s);
return tcg_const_i32(offset);
return tcg_constant_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
offset += (int16_t)read_im16(env, s);
return tcg_const_i32(offset);
return tcg_constant_i32(offset);
case 3: /* pc index+displacement. */
return gen_lea_indexed(env, s, NULL_QREG);
case 4: /* Immediate. */
@ -920,7 +916,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
default:
g_assert_not_reached();
}
return tcg_const_i32(offset);
return tcg_constant_i32(offset);
default:
return NULL_QREG;
}
@ -1167,23 +1163,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
}
switch (opsize) {
case OS_BYTE:
tmp = tcg_const_i32((int8_t)read_im8(env, s));
tmp = tcg_constant_i32((int8_t)read_im8(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_WORD:
tmp = tcg_const_i32((int16_t)read_im16(env, s));
tmp = tcg_constant_i32((int16_t)read_im16(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_LONG:
tmp = tcg_const_i32(read_im32(env, s));
tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_SINGLE:
tmp = tcg_const_i32(read_im32(env, s));
tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_extf32(cpu_env, fp, tmp);
break;
case OS_DOUBLE:
t64 = tcg_const_i64(read_im64(env, s));
t64 = tcg_constant_i64(read_im64(env, s));
gen_helper_extf64(cpu_env, fp, t64);
break;
case OS_EXTENDED:
@ -1191,9 +1187,9 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
tmp = tcg_const_i32(read_im32(env, s) >> 16);
tmp = tcg_constant_i32(read_im32(env, s) >> 16);
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
t64 = tcg_const_i64(read_im64(env, s));
t64 = tcg_constant_i64(read_im64(env, s));
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
break;
case OS_PACKED:
@ -1253,7 +1249,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
goto done;
case 10: /* PL */
case 11: /* MI */
c->v2 = tcg_const_i32(0);
c->v2 = tcg_constant_i32(0);
c->v1 = tmp = tcg_temp_new();
tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
@ -1269,7 +1265,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
}
}
c->v2 = tcg_const_i32(0);
c->v2 = tcg_constant_i32(0);
switch (cond) {
case 0: /* T */
@ -1631,8 +1627,8 @@ static void bcd_add(TCGv dest, TCGv src)
* = result with some possible exceeding 0x6
*/
t0 = tcg_const_i32(0x066);
tcg_gen_add_i32(t0, t0, src);
t0 = tcg_temp_new();
tcg_gen_addi_i32(t0, src, 0x066);
t1 = tcg_temp_new();
tcg_gen_add_i32(t1, t0, dest);
@ -1818,7 +1814,8 @@ DISAS_INSN(nbcd)
SRC_EA(env, src, OS_BYTE, 0, &addr);
dest = tcg_const_i32(0);
dest = tcg_temp_new();
tcg_gen_movi_i32(dest, 0);
bcd_sub(dest, src);
DEST_EA(env, insn, OS_BYTE, dest, &addr);
@ -1896,8 +1893,8 @@ DISAS_INSN(bitop_reg)
else
tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
tmp = tcg_const_i32(1);
tcg_gen_shl_i32(tmp, tmp, src2);
tmp = tcg_temp_new();
tcg_gen_shl_i32(tmp, tcg_constant_i32(1), src2);
tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
@ -1999,7 +1996,7 @@ DISAS_INSN(movem)
addr = tcg_temp_new();
tcg_gen_mov_i32(addr, tmp);
incr = tcg_const_i32(opsize_bytes(opsize));
incr = tcg_constant_i32(opsize_bytes(opsize));
if (is_load) {
/* memory to register */
@ -2235,13 +2232,13 @@ DISAS_INSN(arith_im)
opsize = insn_opsize(insn);
switch (opsize) {
case OS_BYTE:
im = tcg_const_i32((int8_t)read_im8(env, s));
im = tcg_constant_i32((int8_t)read_im8(env, s));
break;
case OS_WORD:
im = tcg_const_i32((int16_t)read_im16(env, s));
im = tcg_constant_i32((int16_t)read_im16(env, s));
break;
case OS_LONG:
im = tcg_const_i32(read_im32(env, s));
im = tcg_constant_i32(read_im32(env, s));
break;
default:
g_assert_not_reached();
@ -2393,7 +2390,6 @@ DISAS_INSN(cas2w)
{
uint16_t ext1, ext2;
TCGv addr1, addr2;
TCGv regs;
/* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
@ -2425,13 +2421,13 @@ DISAS_INSN(cas2w)
* Dc2 = (R2)
*/
regs = tcg_const_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
TCGv regs = tcg_constant_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
gen_helper_cas2w(cpu_env, regs, addr1, addr2);
}
@ -2475,10 +2471,10 @@ DISAS_INSN(cas2l)
* Dc2 = (R2)
*/
regs = tcg_const_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
regs = tcg_constant_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
} else {
@ -2552,7 +2548,7 @@ DISAS_INSN(negx)
* (X, N) = -(src + X);
*/
z = tcg_const_i32(0);
z = tcg_constant_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
@ -2597,8 +2593,7 @@ DISAS_INSN(clr)
int opsize;
TCGv zero;
zero = tcg_const_i32(0);
zero = tcg_constant_i32(0);
opsize = insn_opsize(insn);
DEST_EA(env, insn, opsize, zero, NULL);
gen_logic_cc(s, zero, opsize);
@ -2934,7 +2929,7 @@ DISAS_INSN(jump)
}
if ((insn & 0x40) == 0) {
/* jsr */
gen_push(s, tcg_const_i32(s->pc));
gen_push(s, tcg_constant_i32(s->pc));
}
gen_jmp(s, tmp);
}
@ -2959,7 +2954,7 @@ DISAS_INSN(addsubq)
if (imm == 0) {
imm = 8;
}
val = tcg_const_i32(imm);
val = tcg_constant_i32(imm);
dest = tcg_temp_new();
tcg_gen_mov_i32(dest, src);
if ((insn & 0x38) == 0x08) {
@ -3003,7 +2998,7 @@ DISAS_INSN(branch)
}
if (op == 1) {
/* bsr */
gen_push(s, tcg_const_i32(s->pc));
gen_push(s, tcg_constant_i32(s->pc));
}
if (op > 1) {
/* Bcc */
@ -3076,7 +3071,7 @@ DISAS_INSN(suba)
static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
TCGv tmp;
TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@ -3085,14 +3080,15 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
* (X, N) = dest - (src + X);
*/
tmp = tcg_const_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
zero = tcg_constant_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, zero, QREG_CC_X, zero);
tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, zero, QREG_CC_N, QREG_CC_X);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
/* Compute signed-overflow for subtract. */
tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
@ -3151,9 +3147,10 @@ DISAS_INSN(mov3q)
int val;
val = (insn >> 9) & 7;
if (val == 0)
if (val == 0) {
val = -1;
src = tcg_const_i32(val);
}
src = tcg_constant_i32(val);
gen_logic_cc(s, src, OS_LONG);
DEST_EA(env, insn, OS_LONG, src, NULL);
}
@ -3279,7 +3276,7 @@ DISAS_INSN(adda)
static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
TCGv tmp;
TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@ -3288,13 +3285,14 @@ static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
* (X, N) = src + dest + X;
*/
tmp = tcg_const_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
zero = tcg_constant_i32(0);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, zero, dest, zero);
tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, zero);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
/* Compute signed-overflow for addition. */
tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
@ -3430,7 +3428,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
/* Note that C=0 if shift count is 0, and we get that for free. */
} else {
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
@ -3452,7 +3450,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
* V = ((s ^ t) & (-1 << (bits - 1))) != 0
*/
if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
TCGv_i64 tt = tcg_const_i64(32);
TCGv_i64 tt = tcg_constant_i64(32);
/* if shift is greater than 32, use 32 */
tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
/* Sign extend the input to 64 bits; re-do the shift. */
@ -3633,7 +3631,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
{
TCGv X, shl, shr, shx, sz, zero;
sz = tcg_const_i32(size);
sz = tcg_constant_i32(size);
shr = tcg_temp_new();
shl = tcg_temp_new();
@ -3644,7 +3642,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
/* shx = shx < 0 ? size : shx; */
zero = tcg_const_i32(0);
zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
} else {
tcg_gen_mov_i32(shr, shift); /* shr = shift */
@ -3723,7 +3721,7 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
/* if shift == 0, register and X are not affected */
zero = tcg_const_i32(0);
zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
@ -3741,7 +3739,7 @@ DISAS_INSN(rotate_im)
tmp = 8;
}
shift = tcg_const_i32(tmp);
shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(DREG(insn, 0), shift, left, 32);
} else {
@ -3766,7 +3764,7 @@ DISAS_INSN(rotate8_im)
tmp = 8;
}
shift = tcg_const_i32(tmp);
shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(reg, shift, left, 8);
} else {
@ -3790,7 +3788,7 @@ DISAS_INSN(rotate16_im)
tmp = 8;
}
shift = tcg_const_i32(tmp);
shift = tcg_constant_i32(tmp);
if (insn & 8) {
rotate(reg, shift, left, 16);
} else {
@ -3905,7 +3903,7 @@ DISAS_INSN(rotate_mem)
SRC_EA(env, src, OS_WORD, 0, &addr);
shift = tcg_const_i32(1);
shift = tcg_constant_i32(1);
if (insn & 0x0200) {
rotate(src, shift, left, 16);
} else {
@ -3999,12 +3997,12 @@ DISAS_INSN(bfext_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
if (is_sign) {
@ -4024,14 +4022,8 @@ DISAS_INSN(bfop_reg)
TCGv src = DREG(insn, 0);
int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
int ofs = extract32(ext, 6, 5); /* big bit-endian */
TCGv mask, tofs, tlen;
tofs = NULL;
tlen = NULL;
if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
tofs = tcg_temp_new();
tlen = tcg_temp_new();
}
TCGv mask, tofs = NULL, tlen = NULL;
bool is_bfffo = (insn & 0x0f00) == 0x0d00;
if ((ext & 0x820) == 0) {
/* Immediate width and offset. */
@ -4042,45 +4034,49 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
}
tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
mask = tcg_const_i32(ror32(maski, ofs));
if (tofs) {
tcg_gen_movi_i32(tofs, ofs);
tcg_gen_movi_i32(tlen, len);
mask = tcg_constant_i32(ror32(maski, ofs));
if (is_bfffo) {
tofs = tcg_constant_i32(ofs);
tlen = tcg_constant_i32(len);
}
} else {
TCGv tmp = tcg_temp_new();
mask = tcg_temp_new();
if (ext & 0x20) {
/* Variable width */
tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
tcg_gen_andi_i32(tmp, tmp, 31);
mask = tcg_const_i32(0x7fffffffu);
tcg_gen_shr_i32(mask, mask, tmp);
if (tlen) {
tcg_gen_shr_i32(mask, tcg_constant_i32(0x7fffffffu), tmp);
if (is_bfffo) {
tlen = tcg_temp_new();
tcg_gen_addi_i32(tlen, tmp, 1);
}
} else {
/* Immediate width */
mask = tcg_const_i32(0x7fffffffu >> (len - 1));
if (tlen) {
tcg_gen_movi_i32(tlen, len);
tcg_gen_movi_i32(mask, 0x7fffffffu >> (len - 1));
if (is_bfffo) {
tlen = tcg_constant_i32(len);
}
}
if (ext & 0x800) {
/* Variable offset */
tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotr_i32(mask, mask, tmp);
if (tofs) {
tcg_gen_mov_i32(tofs, tmp);
if (is_bfffo) {
tofs = tmp;
}
} else {
/* Immediate offset (and variable width) */
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotri_i32(mask, mask, ofs);
if (tofs) {
tcg_gen_movi_i32(tofs, ofs);
if (is_bfffo) {
tofs = tcg_constant_i32(ofs);
}
}
}
@ -4122,12 +4118,12 @@ DISAS_INSN(bfop_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
switch (insn & 0x0f00) {
@ -4239,12 +4235,12 @@ DISAS_INSN(bfins_mem)
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
len = tcg_constant_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
@ -4377,7 +4373,7 @@ DISAS_INSN(move16_mem)
TCGv reg, addr;
reg = AREG(insn, 0);
addr = tcg_const_i32(read_im32(env, s));
addr = tcg_constant_i32(read_im32(env, s));
if ((insn >> 3) & 1) {
/* MOVE16 (xxx).L, (Ay) */
@ -4567,14 +4563,14 @@ DISAS_INSN(cf_movec)
} else {
reg = DREG(ext, 12);
}
gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg);
gen_exit_tb(s);
}
DISAS_INSN(m68k_movec)
{
uint16_t ext;
TCGv reg;
TCGv reg, creg;
if (IS_USER(s)) {
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
@ -4588,10 +4584,11 @@ DISAS_INSN(m68k_movec)
} else {
reg = DREG(ext, 12);
}
creg = tcg_constant_i32(ext & 0xfff);
if (insn & 1) {
gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
gen_helper_m68k_movec_to(cpu_env, creg, reg);
} else {
gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
gen_helper_m68k_movec_from(reg, cpu_env, creg);
}
gen_exit_tb(s);
}
@ -4642,7 +4639,7 @@ DISAS_INSN(pflush)
return;
}
opmode = tcg_const_i32((insn >> 3) & 3);
opmode = tcg_constant_i32((insn >> 3) & 3);
gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
}
@ -4654,7 +4651,7 @@ DISAS_INSN(ptest)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
is_read = tcg_const_i32((insn >> 5) & 1);
is_read = tcg_constant_i32((insn >> 5) & 1);
gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
}
#endif
@ -4824,7 +4821,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
tmp = tcg_const_i32(read_im32(env, s));
tmp = tcg_constant_i32(read_im32(env, s));
gen_store_fcr(s, tmp, mask);
return;
}
@ -4961,7 +4958,7 @@ DISAS_INSN(fpu)
case 2:
if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
/* fmovecr */
TCGv rom_offset = tcg_const_i32(opmode);
TCGv rom_offset = tcg_constant_i32(opmode);
cpu_dest = gen_fp_ptr(REG(ext, 7));
gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
return;
@ -5185,7 +5182,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv fpsr;
c->v2 = tcg_const_i32(0);
c->v2 = tcg_constant_i32(0);
/* TODO: Raise BSUN exception. */
fpsr = tcg_temp_new();
gen_load_fcr(s, fpsr, M68K_FPSR);
@ -5405,7 +5402,7 @@ DISAS_INSN(fsave)
if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
/* always write IDLE */
TCGv idle = tcg_const_i32(0x41000000);
TCGv idle = tcg_constant_i32(0x41000000);
DEST_EA(env, insn, OS_LONG, idle, NULL);
} else {
disas_undef(env, s, insn);
@ -5535,7 +5532,7 @@ DISAS_INSN(mac)
/* Skip the accumulate if the value is already saturated. */
l1 = gen_new_label();
tmp = tcg_temp_new();
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
gen_op_jmp_nz32(tmp, l1);
}
#endif
@ -5546,11 +5543,11 @@ DISAS_INSN(mac)
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
gen_helper_macsats(cpu_env, tcg_const_i32(acc));
gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
else
gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
@ -5569,7 +5566,7 @@ DISAS_INSN(mac)
/* Skip the accumulate if the value is already saturated. */
l1 = gen_new_label();
tmp = tcg_temp_new();
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc));
gen_op_jmp_nz32(tmp, l1);
}
#endif
@ -5578,18 +5575,18 @@ DISAS_INSN(mac)
else
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
gen_helper_macsats(cpu_env, tcg_const_i32(acc));
gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
else
gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
if (l1 != -1)
gen_set_label(l1);
#endif
}
gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc));
if (insn & 0x30) {
TCGv rw;
@ -5639,8 +5636,8 @@ DISAS_INSN(move_mac)
int src;
TCGv dest;
src = insn & 3;
dest = tcg_const_i32((insn >> 9) & 3);
gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
dest = tcg_constant_i32((insn >> 9) & 3);
gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src));
gen_mac_clear_flags();
gen_helper_mac_set_flags(cpu_env, dest);
}
@ -5665,7 +5662,7 @@ DISAS_INSN(from_mext)
TCGv reg;
TCGv acc;
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
gen_helper_get_mac_extf(reg, cpu_env, acc);
else
@ -5700,7 +5697,7 @@ DISAS_INSN(to_mac)
}
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
gen_mac_clear_flags();
gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum));
}
DISAS_INSN(to_macsr)
@ -5723,7 +5720,7 @@ DISAS_INSN(to_mext)
TCGv val;
TCGv acc;
SRC_EA(env, val, OS_LONG, 0, NULL);
acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
gen_helper_set_mac_extf(cpu_env, val, acc);
else if (s->env->macsr & MACSR_SU)

1
target/microblaze/cpu-param.h
View File

@ -28,6 +28,5 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 3
#endif

2
target/microblaze/cpu.h
View File

@ -394,7 +394,7 @@ void mb_tcg_init(void);
#define MMU_NOMMU_IDX 0
#define MMU_KERNEL_IDX 1
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
/* See NB_MMU_MODES in cpu-defs.h. */
#include "exec/cpu-all.h"

1
target/mips/cpu-param.h
View File

@ -29,6 +29,5 @@
#define TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN 12
#endif
#define NB_MMU_MODES 4
#endif

12
target/mips/tcg/micromips_translate.c.inc
View File

@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
gen_base_offset_addr(ctx, t0, base, offset);
t1 = tcg_const_tl(reglist);
t2 = tcg_const_i32(ctx->mem_idx);
t1 = tcg_constant_tl(reglist);
t2 = tcg_constant_i32(ctx->mem_idx);
save_cpu_state(ctx, 1);
switch (opc) {
@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
break;
#endif
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free_i32(t2);
}
@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
break;
#endif
}
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
tcg_temp_free(t0);
}
break;
#endif
@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
* mode.
*/
ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
case EI:
@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
*/
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
tcg_temp_free(t0);
}
break;
default:

9
target/mips/tcg/msa_translate.c
View File

@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
/* if some bit is non-zero then some element is zero */
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(tresult, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_load_gpr(telm, a->ws);
gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
tcg_temp_free(telm);
return true;
}
@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);
tcg_temp_free(telm);
return true;
}
@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);
tcg_temp_free(taddr);
return true;
}

55
target/mips/tcg/mxu_translate.c
View File

@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx)
} else if (XRa == 16) {
gen_store_mxu_cr(t0);
}
tcg_temp_free(t0);
}
/*
@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
}
gen_store_gpr(t0, Rb);
tcg_temp_free(t0);
}
/*
@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
}
gen_store_mxu_gpr(t0, XRa);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
/*
@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
}
/*
@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
}
/*
@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
gen_store_mxu_gpr(t0, XRd);
gen_store_mxu_gpr(t1, XRa);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
tcg_temp_free(t4);
tcg_temp_free(t5);
tcg_temp_free(t6);
tcg_temp_free(t7);
}
/*
@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
gen_store_mxu_gpr(t1, XRa);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@ -1101,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do half-word-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
/* the left half-word first */
tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
}
@ -1198,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do byte-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
int32_t i;
/* the leftmost byte (byte 3) first */
@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
tcg_temp_free(t1);
tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
tcg_temp_free(t1);
tcg_temp_free(t0);
}
}
@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 24);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN2:
@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 16);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN3:
@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 8);
tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN4:
@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
}
gen_set_label(l_exit);
tcg_temp_free(t_mxu_cr);
}
return true;

143
target/mips/tcg/nanomips_translate.c.inc
View File

@ -1005,13 +1005,9 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
}
gen_store_gpr(tmp1, reg1);
tcg_temp_free(tmp1);
gen_store_gpr(tmp2, reg2);
tcg_temp_free(tmp2);
tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_temp_free_i64(tval);
tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
tcg_temp_free(taddr);
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
@ -1084,9 +1080,6 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
/* adjust stack pointer */
gen_adjust_sp(ctx, -u);
tcg_temp_free(t0);
tcg_temp_free(va);
}
static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
@ -1110,9 +1103,6 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
/* adjust stack pointer */
gen_adjust_sp(ctx, u);
tcg_temp_free(t0);
tcg_temp_free(va);
}
static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
@ -1232,8 +1222,6 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16;
}
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
@ -1358,7 +1346,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
tcg_temp_free(t0);
#endif
} else {
gen_slt(ctx, OPC_SLTU, rd, rs, rt);
@ -1381,10 +1368,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
/* operands of same sign, result different sign */
tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
break;
case NM_MUL:
@ -1427,7 +1410,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3));
tcg_temp_free(t0);
}
break;
case NM_D_E_MT_VPE:
@ -1467,8 +1449,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
tcg_temp_free(t0);
}
break;
case NM_FORK:
@ -1480,8 +1460,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
gen_helper_fork(t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
case NM_MFTR:
@ -1508,7 +1486,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
gen_helper_yield(t0, cpu_env, t0);
gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
break;
#endif
@ -1557,11 +1534,6 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free_i32(t0);
tcg_temp_free(v0_t);
tcg_temp_free(v1_t);
}
@ -1682,10 +1654,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(v0_t);
}
static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
@ -1802,8 +1770,6 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free_i32(t0);
}
static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
@ -1855,10 +1821,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
tcg_temp_free_i64(t2);
}
break;
case NM_MULT:
@ -1878,8 +1842,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_muls2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
}
break;
case NM_EXTRV_W:
@ -1915,10 +1877,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
tcg_temp_free_i64(t2);
}
break;
case NM_MULTU:
@ -1938,8 +1898,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mulu2_i32(t2, t3, t2, t3);
tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
}
break;
case NM_EXTRV_R_W:
@ -1982,10 +1940,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
tcg_temp_free_i64(t2);
}
break;
case NM_EXTRV_RS_W:
@ -2027,10 +1983,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
tcg_temp_free_i64(t3);
gen_move_low32(cpu_LO[acc], t2);
gen_move_high32(cpu_HI[acc], t2);
tcg_temp_free_i64(t2);
}
break;
case NM_EXTRV_S_H:
@ -2045,12 +1999,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(v0_t);
tcg_temp_free(v1_t);
}
static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
@ -2162,7 +2110,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_load_gpr(tv0, rt);
gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
gen_store_gpr(v0_t, ret);
tcg_temp_free(tv0);
}
break;
case NM_RADDU_W_QB:
@ -2188,9 +2135,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(v0_t);
tcg_temp_free(t0);
}
static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
@ -2243,8 +2187,6 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
tcg_temp_free(rs_t);
}
@ -2304,7 +2246,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
case NM_EI:
@ -2317,7 +2258,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
case NM_RDPGPR:
@ -2374,7 +2314,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
/* Unconditional branch */
} else if (rt == 0 && imm != 0) {
/* Treat as NOP */
goto out;
return;
} else {
cond = TCG_COND_EQ;
}
@ -2384,12 +2324,12 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
check_nms(ctx);
if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
gen_reserved_instruction(ctx);
goto out;
return;
} else if (rt == 0 && opc == NM_BBEQZC) {
/* Unconditional branch */
} else if (rt == 0 && opc == NM_BBNEZC) {
/* Treat as NOP */
goto out;
return;
} else {
tcg_gen_shri_tl(t0, t0, imm);
tcg_gen_andi_tl(t0, t0, 1);
@ -2404,7 +2344,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
case NM_BNEIC:
if (rt == 0 && imm == 0) {
/* Treat as NOP */
goto out;
return;
} else if (rt == 0 && imm != 0) {
/* Unconditional branch */
} else {
@ -2434,7 +2374,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Immediate Value Compact branch");
gen_reserved_instruction(ctx);
goto out;
return;
}
/* branch completion */
@ -2455,10 +2395,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
@ -2488,9 +2424,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
/* unconditional branch to register */
tcg_gen_mov_tl(cpu_PC, btarget);
tcg_gen_lookup_and_goto_ptr();
tcg_temp_free(t0);
tcg_temp_free(t1);
}
/* nanoMIPS Branches */
@ -2540,14 +2473,12 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
gen_load_gpr(tbase, rt);
tcg_gen_movi_tl(toffset, offset);
gen_op_addr_add(ctx, btarget, tbase, toffset);
tcg_temp_free(tbase);
tcg_temp_free(toffset);
}
break;
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
goto out;
return;
}
if (bcond_compute == 0) {
@ -2559,7 +2490,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact branch/jump");
gen_reserved_instruction(ctx);
goto out;
return;
}
} else {
/* Conditional compact branch */
@ -2620,7 +2551,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
default:
MIPS_INVAL("Compact conditional branch/jump");
gen_reserved_instruction(ctx);
goto out;
return;
}
/* branch completion */
@ -2633,10 +2564,6 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@ -2664,15 +2591,12 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
default:
MIPS_INVAL("cp1 cond branch");
gen_reserved_instruction(ctx);
goto out;
return;
}
tcg_gen_trunc_i64_tl(bcond, t0);
ctx->btarget = btarget;
out:
tcg_temp_free_i64(t0);
}
@ -2709,7 +2633,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
break;
default:
gen_reserved_instruction(ctx);
goto out;
return;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@ -2799,10 +2723,6 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
gen_reserved_instruction(ctx);
break;
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
@ -3439,21 +3359,19 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 0:
/* PRECR_SRA_PH_W */
{
TCGv_i32 sa_t = tcg_const_i32(rd);
TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
tcg_temp_free_i32(sa_t);
}
break;
case 1:
/* PRECR_SRA_R_PH_W */
{
TCGv_i32 sa_t = tcg_const_i32(rd);
TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
tcg_temp_free_i32(sa_t);
}
break;
}
@ -3536,8 +3454,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm);
gen_helper_shilo(tv0, tv1, cpu_env);
tcg_temp_free(tv1);
tcg_temp_free(tv0);
}
break;
case NM_MULEQ_S_W_PHL:
@ -3652,10 +3568,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(v2_t);
tcg_temp_free(v1_t);
tcg_temp_free(t0);
}
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
@ -3827,7 +3739,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
tcg_temp_free(t0);
}
break;
case NM_SWPC48:
@ -3844,9 +3755,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
default:
@ -3908,8 +3816,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rs);
tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm);
gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
break;
case NM_ADDIUNEG:
@ -3958,18 +3864,15 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_nms(ctx);
if (rt != 0) {
TCGv t0 = tcg_temp_new();
TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
<< 1);
TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
TCGv_i32 shift =
tcg_constant_i32(extract32(ctx->opcode, 0, 5));
TCGv_i32 shiftx =
tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
TCGv_i32 stripe =
tcg_constant_i32(extract32(ctx->opcode, 6, 1));
gen_load_gpr(t0, rs);
gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
tcg_temp_free(t0);
tcg_temp_free_i32(shift);
tcg_temp_free_i32(shiftx);
tcg_temp_free_i32(stripe);
}
break;
case NM_P_INS:
@ -4239,8 +4142,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
MO_UNALN);
break;
}
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
case NM_P_LL:
@ -4432,8 +4333,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
counter++;
}
tcg_temp_free(va);
tcg_temp_free(t1);
}
break;
default:
@ -4454,7 +4353,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
tcg_temp_free(t0);
}
break;
case NM_P_BAL:
@ -4604,9 +4502,8 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_const_tl(ctx->base.pc_next);
TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_temp_free(tmp);
generate_exception_end(ctx, EXCP_AdEL);
return 2;
}
@ -4941,8 +4838,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_mov_tl(cpu_gpr[re], t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
default:

23
target/mips/tcg/octeon_translate.c
View File

@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
ctx->hflags |= MIPS_HFLAG_BC;
ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
ctx->hflags |= MIPS_HFLAG_BDS32;
tcg_temp_free(t0);
return true;
}
@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
gen_load_gpr(t1, a->rt);
tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);
return true;
}
@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);
return true;
}
@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)
}
tcg_gen_ctpop_tl(t0, t0);
gen_store_gpr(t0, a->rd);
tcg_temp_free(t0);
return true;
}
@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
} else {
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
}
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
} else {
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
}
tcg_temp_free(t0);
return true;
}

819
target/mips/tcg/translate.c
View File

File diff suppressed because it is too large Load Diff

7
target/mips/tcg/translate_addr_const.c
View File

@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
tcg_temp_free(t1);
tcg_temp_free(t0);
return true;
}
@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_temp_free(t1);
tcg_temp_free(t0);
return true;
}

45
target/mips/tcg/tx79_translate.c
View File

@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -247,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
return true;
}
c0 = tcg_const_tl(0);
c1 = tcg_const_tl(0xffffffff);
c0 = tcg_constant_tl(0);
c1 = tcg_constant_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
}
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
tcg_temp_free(bx);
tcg_temp_free(ax);
tcg_temp_free(c1);
tcg_temp_free(c0);
return true;
}
@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
gen_store_gpr_hi(t0, a->rt);
tcg_temp_free(t0);
tcg_temp_free(addr);
return true;
}
@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
tcg_temp_free(addr);
tcg_temp_free(t0);
return true;
}
@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(t0, a->rs); /* a1 */
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
tcg_temp_free(t0);
tcg_temp_free(b0);
tcg_temp_free(a0);
return true;
}
@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
tcg_temp_free(ax);
return true;
}

4
target/mips/tcg/vr54xx_translate.c
View File

@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
gen_helper_mult_acc(t0, cpu_env, t0, t1);
gen_store_gpr(t0, a->rd);
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}

1
target/nios2/cpu-param.h
View File

@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define NB_MMU_MODES 2
#endif

1
target/openrisc/cpu-param.h
View File

@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 3
#endif

1
target/ppc/cpu-param.h
View File

@ -32,6 +32,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 10
#endif

4
target/ppc/power8-pmu-regs.c.inc
View File

@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t_sprn = tcg_const_i32(sprn);
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t_sprn = tcg_const_i32(sprn);
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);

148
target/ppc/translate.c
View File

@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
t1 = tcg_const_i32(error);
t0 = tcg_constant_i32(excp);
t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(cpu_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
TCGv_i32 t0;
gen_update_nip(ctx, nip);
t0 = tcg_const_i32(excp);
t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
static void spr_load_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_const_i32(sprn);
TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_load_dump_spr(cpu_env, t0);
#endif
}
@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
static void spr_store_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_const_i32(sprn);
TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_store_dump_spr(cpu_env, t0);
#endif
}
@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn);
TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
}
void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
TCGv_i32 t1 = tcg_const_i32(bit);
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
TCGv_i32 t1 = tcg_constant_i32(bit);
TCGv_i32 t2 = tcg_constant_i32(sprn);
TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
}
@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
TCGv_i32 t1 = tcg_const_i32(bit);
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
TCGv_i32 t1 = tcg_constant_i32(bit);
TCGv_i32 t2 = tcg_constant_i32(sprn);
TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
}
@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_tl(arg1);
TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
}
@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_tl(arg1);
TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
}
@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx)
tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
tcg_gen_andi_tl(t0, t0, mask);
zr = tcg_const_tl(0);
zr = tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
cpu_gpr[rB(ctx->opcode)]);
@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ca32, ca);
}
} else {
TCGv zero = tcg_const_tl(0);
TCGv zero = tcg_constant_tl(0);
if (add_ca) {
tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv t0 = tcg_const_tl(const_val); \
TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
ca, glue(ca, 32), \
@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
TCGv c = tcg_const_tl(SIMM(ctx->opcode));
TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
}
@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
#define GEN_DIVE(name, hlpr, compute_ov) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0 = tcg_const_i32(compute_ov); \
TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_rem_i32(t3, t0, t1);
tcg_gen_ext_i32_tl(ret, t3);
} else {
TCGv_i32 t2 = tcg_const_i32(1);
TCGv_i32 t3 = tcg_const_i32(0);
TCGv_i32 t2 = tcg_constant_i32(1);
TCGv_i32 t3 = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i32(t3, t0, t1);
tcg_gen_extu_i32_tl(ret, t3);
@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_rem_i64(ret, t0, t1);
} else {
TCGv_i64 t2 = tcg_const_i64(1);
TCGv_i64 t3 = tcg_const_i64(0);
TCGv_i64 t2 = tcg_constant_i64(1);
TCGv_i64 t3 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i64(ret, t0, t1);
}
@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
zero = tcg_const_tl(0);
zero = tcg_constant_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv t0 = tcg_const_tl(const_val); \
TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
/* subfic */
static void gen_subfic(DisasContext *ctx)
{
TCGv c = tcg_const_tl(SIMM(ctx->opcode));
TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, 0, 1, 0, 0);
}
@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx)
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
{
TCGv zero = tcg_const_tl(0);
TCGv zero = tcg_constant_tl(0);
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
zero, 0, 0, compute_ov, Rc(ctx->opcode));
}
@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
static void gen_pause(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(0);
TCGv_i32 t0 = tcg_constant_i32(0);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rD(ctx->opcode));
t1 = tcg_constant_i32(rD(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_lmw(cpu_env, t0, t1);
}
@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rS(ctx->opcode));
t1 = tcg_constant_i32(rS(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_stmw(cpu_env, t0, t1);
}
@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_register(ctx, t0);
t1 = tcg_const_i32(nb);
t2 = tcg_const_i32(start);
t1 = tcg_constant_i32(nb);
t2 = tcg_constant_i32(start);
gen_helper_lsw(cpu_env, t0, t1, t2);
}
@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
t1 = tcg_const_i32(rD(ctx->opcode));
t2 = tcg_const_i32(rA(ctx->opcode));
t3 = tcg_const_i32(rB(ctx->opcode));
t1 = tcg_constant_i32(rD(ctx->opcode));
t2 = tcg_constant_i32(rA(ctx->opcode));
t3 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_lswx(cpu_env, t0, t1, t2, t3);
}
@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx)
if (nb == 0) {
nb = 32;
}
t1 = tcg_const_i32(nb);
t2 = tcg_const_i32(rS(ctx->opcode));
t1 = tcg_constant_i32(nb);
t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx)
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, cpu_xer);
tcg_gen_andi_i32(t1, t1, 0x7F);
t2 = tcg_const_i32(rS(ctx->opcode));
t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx)
* to occur.
*/
if (wc == 0) {
TCGv_i32 t0 = tcg_const_i32(1);
TCGv_i32 t0 = tcg_constant_i32(1);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
/* Stop translation, as the CPU is supposed to sleep from now */
@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_DOZE);
t = tcg_constant_i32(PPC_PM_DOZE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_NAP);
t = tcg_constant_i32(PPC_PM_NAP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_STOP);
t = tcg_constant_i32(PPC_PM_STOP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_SLEEP);
t = tcg_constant_i32(PPC_PM_SLEEP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_RVWINKLE);
t = tcg_constant_i32(PPC_PM_RVWINKLE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
t0 = tcg_const_i32(TO(ctx->opcode));
t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
t0 = tcg_const_tl(SIMM(ctx->opcode));
t1 = tcg_const_i32(TO(ctx->opcode));
t0 = tcg_constant_tl(SIMM(ctx->opcode));
t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
t0 = tcg_const_i32(TO(ctx->opcode));
t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
t0 = tcg_const_tl(SIMM(ctx->opcode));
t1 = tcg_const_i32(TO(ctx->opcode));
t0 = tcg_constant_tl(SIMM(ctx->opcode));
t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
#endif
@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
}
@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
}
@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx)
case 1:
case 2:
{
TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
t0, cpu_gpr[rA(ctx->opcode)]);
}
@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx)
case 1:
case 2:
{
TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
}
@ -5875,12 +5877,10 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
CHK_SV(ctx);
if (rA(ctx->opcode)) {
t0 = tcg_temp_new();
tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
} else {
t0 = tcg_const_tl(0);
t0 = cpu_gpr[rB(ctx->opcode)];
}
tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
gen_helper_booke206_tlbsx(cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@ -5983,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx)
/* dlmzb */
static void gen_dlmzb(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
}

44
target/ppc/translate/fixedpoint-impl.c.inc
View File

@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
{
const uint64_t carry_bits = 0x1111111111111111ULL;
TCGv t0, t1, carry, zero = tcg_constant_tl(0);
const target_ulong carry_bits = (target_ulong)-1 / 0xf;
TCGv in1, in2, carryl, carryh, tmp;
TCGv zero = tcg_constant_tl(0);
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
t0 = tcg_temp_new();
t1 = tcg_const_tl(0);
carry = tcg_const_tl(0);
in1 = cpu_gpr[a->ra];
in2 = cpu_gpr[a->rb];
tmp = tcg_temp_new();
carryl = tcg_temp_new();
carryh = tcg_temp_new();
for (int i = 0; i < 16; i++) {
tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
tcg_gen_andi_tl(t0, t0, 0xf);
tcg_gen_add_tl(t1, t1, t0);
/* Addition with carry. */
tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
/* Addition without carry. */
tcg_gen_xor_tl(tmp, in1, in2);
/* Difference between the two is carry in to each bit. */
tcg_gen_xor_tl(carryl, carryl, tmp);
tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
tcg_gen_andi_tl(t0, t0, 0xf);
tcg_gen_add_tl(t1, t1, t0);
/*
* The carry-out that we're looking for is the carry-in to
* the next nibble. Shift the double-word down one nibble,
* which puts all of the bits back into one word.
*/
tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
tcg_gen_andi_tl(t1, t1, 0x10);
tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
tcg_gen_shli_tl(t0, t1, i * 4);
tcg_gen_or_tl(carry, carry, t0);
}
tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
/* Invert, isolate the carry bits, and produce 6's. */
tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
return true;
}

26
target/ppc/translate/fp-impl.c.inc
View File

@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpo(cpu_env, t0, t1, crf);
@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpu(cpu_env, t0, t1, crf);
@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
tmask = tcg_const_i32(1 << nibble);
tmask = tcg_constant_i32(1 << nibble);
gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
}
@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
TCGv_i32 t0;
t0 = tcg_const_i32(crb);
gen_helper_fpscr_clrbit(cpu_env, t0);
gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
TCGv_i32 t0;
t0 = tcg_const_i32(crb);
gen_helper_fpscr_setbit(cpu_env, t0);
gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
if (l) {
t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
if (!l) {
t0 = tcg_constant_i32(flm << (w * 8));
} else if (ctx->insns_flags2 & PPC2_ISA205) {
t0 = tcg_constant_i32(0xffff);
} else {
t0 = tcg_const_i32(flm << (w * 8));
t0 = tcg_constant_i32(0xff);
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
return;
}
sh = (8 * w) + 7 - bf;
t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_const_i32(1 << sh);
t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_constant_i32(1 << sh);
gen_helper_store_fpscr(cpu_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);

130
target/ppc/translate/vmx-impl.c.inc
View File

@ -171,53 +171,56 @@ static void gen_mtvscr(DisasContext *ctx)
gen_helper_mtvscr(cpu_env, val);
}
static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
{
TCGv_i64 t0;
TCGv_i64 t1;
TCGv_i64 t2;
TCGv_i64 avr;
TCGv_i64 ten, z;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
avr = tcg_temp_new_i64();
ten = tcg_constant_i64(10);
z = tcg_constant_i64(0);
if (add_cin) {
get_avr64(avr, rA(ctx->opcode), false);
tcg_gen_mulu2_i64(t0, t1, avr, ten);
get_avr64(avr, rB(ctx->opcode), false);
tcg_gen_andi_i64(t2, avr, 0xF);
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z);
set_avr64(rD(ctx->opcode), avr, false);
} else {
get_avr64(avr, rA(ctx->opcode), false);
tcg_gen_mulu2_i64(avr, t2, avr, ten);
set_avr64(rD(ctx->opcode), avr, false);
}
if (ret_carry) {
get_avr64(avr, rA(ctx->opcode), true);
tcg_gen_mulu2_i64(t0, t1, avr, ten);
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z);
set_avr64(rD(ctx->opcode), avr, false);
set_avr64(rD(ctx->opcode), z, true);
} else {
get_avr64(avr, rA(ctx->opcode), true);
tcg_gen_mul_i64(t0, avr, ten);
tcg_gen_add_i64(avr, t0, t2);
set_avr64(rD(ctx->opcode), avr, true);
}
}
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
TCGv_i64 t1; \
TCGv_i64 t2; \
TCGv_i64 avr; \
TCGv_i64 ten, z; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
t2 = tcg_temp_new_i64(); \
avr = tcg_temp_new_i64(); \
ten = tcg_const_i64(10); \
z = tcg_const_i64(0); \
\
if (add_cin) { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
get_avr64(avr, rB(ctx->opcode), false); \
tcg_gen_andi_i64(t2, avr, 0xF); \
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
} else { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(avr, t2, avr, ten); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
\
if (ret_carry) { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
set_avr64(rD(ctx->opcode), z, true); \
} else { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mul_i64(t0, avr, ten); \
tcg_gen_add_i64(avr, t0, t2); \
set_avr64(rD(ctx->opcode), avr, true); \
} \
} \
static void glue(gen_, name)(DisasContext *ctx) \
{ gen_vx_vmul10(ctx, add_cin, ret_carry); }
GEN_VX_VMUL10(vmul10uq, 0, 0);
GEN_VX_VMUL10(vmul10euq, 1, 0);
@ -903,7 +906,6 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_const_i64(0);
get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true);
@ -914,7 +916,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
if (alg) {
t1 = tcg_temp_new_i64();
tcg_gen_sari_i64(t1, lo, 63);
} else {
t1 = zero;
}
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
} else {
@ -1619,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \
@ -1960,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx)
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
sh = tcg_const_i32(VSH(ctx->opcode));
sh = tcg_constant_i32(VSH(ctx->opcode));
gen_helper_vsldoi(rd, ra, rb, sh);
}
@ -2231,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
{
TCGv_i64 rt, vrb, mask;
rt = tcg_const_i64(0);
vrb = tcg_temp_new_i64();
TCGv_i64 r[2], mask;
r[0] = tcg_temp_new_i64();
r[1] = tcg_temp_new_i64();
mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
for (int i = 0; i < 2; i++) {
get_avr64(vrb, a->vrb, i);
get_avr64(r[i], a->vrb, i);
if (a->mp) {
tcg_gen_and_i64(vrb, mask, vrb);
tcg_gen_and_i64(r[i], mask, r[i]);
} else {
tcg_gen_andc_i64(vrb, mask, vrb);
tcg_gen_andc_i64(r[i], mask, r[i]);
}
tcg_gen_ctpop_i64(vrb, vrb);
tcg_gen_add_i64(rt, rt, vrb);
tcg_gen_ctpop_i64(r[i], r[i]);
}
tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
tcg_gen_add_i64(r[0], r[0], r[1]);
tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
return true;
}
@ -2569,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
}
@ -2588,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, rb, ps); \
}
@ -2720,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
st_six = tcg_const_i32(rB(ctx->opcode)); \
st_six = tcg_constant_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
}

36
target/ppc/translate/vsx-impl.c.inc
View File

@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
ro = tcg_const_i32(a->rc);
ro = tcg_constant_i32(a->rc);
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
}
@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \
}
@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \
@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(2047);
get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(32767);
tcg_gen_extract_i64(exp, xbh, 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(2047);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
TCGv_i64 conj, disj;
conj = tcg_temp_new_i64();
disj = tcg_const_i64(0);
disj = tcg_temp_new_i64();
tcg_gen_movi_i64(disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
int bit;
TCGv_vec disj, conj;
disj = tcg_const_zeros_vec_matching(t);
conj = tcg_temp_new_vec_matching(t);
disj = tcg_temp_new_vec_matching(t);
tcg_gen_dupi_vec(vece, disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
/* Equivalent functions that can be implemented with a single gen_gvec */
switch (a->imm) {
case 0b00000000: /* true */
case 0b00000000: /* false */
set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
break;

1
target/riscv/cpu-param.h
View File

@ -27,6 +27,5 @@
* - S mode HLV/HLVX/HSV 0b101
* - M mode HLV/HLVX/HSV 0b111
*/
#define NB_MMU_MODES 8
#endif

2
target/rx/cpu-param.h
View File

@ -25,6 +25,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 1
#endif

84
target/rx/translate.c
View File

@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{
TCGv imm, mem;
imm = tcg_const_i32(a->imm);
imm = tcg_constant_i32(a->imm);
mem = tcg_temp_new();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
rx_gen_st(a->sz, imm, mem);
@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
{
TCGv z;
TCGv _imm;
z = tcg_const_i32(0);
_imm = tcg_const_i32(imm);
z = tcg_constant_i32(0);
_imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
_imm, cpu_regs[rd]);
}
@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{
TCGv imm = tcg_const_i32(src2);
TCGv imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm);
}
@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
/* ret = arg1 + arg2 + psw_c */
static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv z;
z = tcg_const_i32(0);
TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
tcg_gen_xor_i32(z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
/* ret = arg1 + arg2 */
static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv z;
z = tcg_const_i32(0);
TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
tcg_gen_xor_i32(z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
/* ret = arg1 - arg2 */
static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv temp;
tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
temp = tcg_temp_new_i32();
tcg_gen_xor_i32(temp, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
/* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
}
static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
{
rx_sub(NULL, arg1, arg2);
}
/* ret = arg1 - arg2 - !psw_c */
/* -> ret = arg1 + ~arg2 + psw_c */
static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
@ -1126,21 +1124,11 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
return true;
}
static void rx_abs(TCGv ret, TCGv arg1)
{
TCGv neg;
TCGv zero;
neg = tcg_temp_new();
zero = tcg_const_i32(0);
tcg_gen_neg_i32(neg, arg1);
tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1);
}
/* abs rd */
/* abs rs, rd */
static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
{
rx_gen_op_rr(rx_abs, a->rd, a->rs);
rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs);
return true;
}
@ -1200,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{
TCGv imm = tcg_const_i32(a->imm);
TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@ -1227,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{
TCGv imm = tcg_const_i32(a->imm);
TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@ -1325,10 +1313,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
done = gen_new_label();
/* if (cpu_regs[a->rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
count = tcg_const_i32(32);
count = tcg_temp_new();
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
tcg_gen_sub_i32(count, count, tmp);
tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
@ -1597,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
static inline void rx_save_pc(DisasContext *ctx)
{
TCGv pc = tcg_const_i32(ctx->base.pc_next);
TCGv pc = tcg_constant_i32(ctx->base.pc_next);
push(pc);
}
@ -1680,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
#define STRING(op) \
do { \
TCGv size = tcg_const_i32(a->sz); \
TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \
} while (0)
@ -1811,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
TCGv imm = tcg_const_i32(a->imm + 1);
TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm);
return true;
}
@ -1821,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{
TCGv tmp, z;
tmp = tcg_temp_new();
z = tcg_const_i32(0);
z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
@ -1843,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
TCGv imm = tcg_const_i32(li(ctx, 0)); \
TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \
cpu_regs[a->rd], imm); \
return true; \
@ -1877,7 +1865,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
TCGv imm = tcg_const_i32(li(ctx, 0));
TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
return true;
}
@ -1974,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
{ \
TCGv mask, mem, addr; \
mem = tcg_temp_new(); \
mask = tcg_const_i32(1 << a->imm); \
mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
return true; \
@ -1983,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _ir) * a) \
{ \
TCGv mask; \
mask = tcg_const_i32(1 << a->imm); \
mask = tcg_constant_i32(1 << a->imm); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@ -1991,10 +1979,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rr) * a) \
{ \
TCGv mask, b; \
mask = tcg_const_i32(1); \
mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
tcg_gen_shl_i32(mask, mask, b); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@ -2002,10 +1990,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rm) * a) \
{ \
TCGv mask, mem, addr, b; \
mask = tcg_const_i32(1); \
mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
tcg_gen_shl_i32(mask, mask, b); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
mem = tcg_temp_new(); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
@ -2128,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{
TCGv imm;
imm = tcg_const_i32(a->imm);
imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr);
return true;
}
@ -2190,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
TCGv vec;
tcg_debug_assert(a->imm < 0x100);
vec = tcg_const_i32(a->imm);
vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec);
ctx->base.is_jmp = DISAS_NORETURN;

1
target/s390x/cpu-param.h
View File

@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define NB_MMU_MODES 4
#endif

208
target/s390x/tcg/translate.c
View File

@ -156,8 +156,6 @@ struct DisasContext {
typedef struct {
TCGCond cond:8;
bool is_64;
bool g1;
bool g2;
union {
struct { TCGv_i64 a, b; } s64;
struct { TCGv_i32 a, b; } s32;
@ -308,8 +306,6 @@ static TCGv_i128 load_freg_128(int reg)
TCGv_i128 r = tcg_temp_new_i128();
tcg_gen_concat_i64_i128(r, l, h);
tcg_temp_free_i64(h);
tcg_temp_free_i64(l);
return r;
}
@ -722,7 +718,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
c->u.s32.a = cc_op;
c->u.s32.b = cc_op;
c->g1 = c->g2 = true;
c->is_64 = false;
return;
}
@ -839,7 +834,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
/* Load up the arguments of the comparison. */
c->is_64 = true;
c->g1 = c->g2 = false;
switch (old_cc_op) {
case CC_OP_LTGT0_32:
c->is_64 = false;
@ -861,13 +855,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_FLOGR:
c->u.s64.a = cc_dst;
c->u.s64.b = tcg_constant_i64(0);
c->g1 = true;
break;
case CC_OP_LTGT_64:
case CC_OP_LTUGTU_64:
c->u.s64.a = cc_src;
c->u.s64.b = cc_dst;
c->g1 = c->g2 = true;
break;
case CC_OP_TM_32:
@ -882,7 +874,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_SUBU:
c->is_64 = true;
c->u.s64.b = tcg_constant_i64(0);
c->g1 = true;
switch (mask) {
case 8 | 2:
case 4 | 1: /* result */
@ -900,7 +891,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_STATIC:
c->is_64 = false;
c->u.s32.a = cc_op;
c->g1 = true;
switch (mask) {
case 0x8 | 0x4 | 0x2: /* cc != 3 */
cond = TCG_COND_NE;
@ -916,7 +906,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
break;
case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
cond = TCG_COND_EQ;
c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
@ -935,7 +924,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
break;
case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
cond = TCG_COND_NE;
c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
@ -959,7 +947,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
default:
/* CC is masked by something else: (8 >> cc) & mask. */
cond = TCG_COND_NE;
c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
c->u.s32.b = tcg_constant_i32(0);
tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
@ -974,24 +961,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
c->cond = cond;
}
static void free_compare(DisasCompare *c)
{
if (!c->g1) {
if (c->is_64) {
tcg_temp_free_i64(c->u.s64.a);
} else {
tcg_temp_free_i32(c->u.s32.a);
}
}
if (!c->g2) {
if (c->is_64) {
tcg_temp_free_i64(c->u.s64.b);
} else {
tcg_temp_free_i32(c->u.s32.b);
}
}
}
/* ====================================================================== */
/* Define the insn format enumeration. */
#define F0(N) FMT_##N,
@ -1092,7 +1061,6 @@ static const DisasFormatInfo format_info[] = {
them, and store them back. See the "in1", "in2", "prep", "wout" sets
of routines below for more details. */
typedef struct {
bool g_out, g_out2, g_in1, g_in2;
TCGv_i64 out, out2, in1, in2;
TCGv_i64 addr1;
TCGv_i128 out_128, in1_128, in2_128;
@ -1292,17 +1260,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
TCGv_i64 z = tcg_constant_i64(0);
tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
tcg_gen_extu_i32_i64(t1, t0);
tcg_temp_free_i32(t0);
tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
per_branch_cond(s, TCG_COND_NE, t1, z);
tcg_temp_free_i64(t1);
}
ret = DISAS_PC_UPDATED;
}
egress:
free_compare(c);
return ret;
}
@ -1462,11 +1427,11 @@ static DisasJumpType op_andi(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
TCGv_i64 t = tcg_temp_new_i64();
assert(!o->g_in2);
tcg_gen_shli_i64(o->in2, o->in2, shift);
tcg_gen_ori_i64(o->in2, o->in2, ~mask);
tcg_gen_and_i64(o->out, o->in1, o->in2);
tcg_gen_shli_i64(t, o->in2, shift);
tcg_gen_ori_i64(t, t, ~mask);
tcg_gen_and_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
@ -1555,7 +1520,6 @@ static void save_link_info(DisasContext *s, DisasOps *o)
tcg_gen_extu_i32_i64(t, cc_op);
tcg_gen_shli_i64(t, t, 28);
tcg_gen_or_i64(o->out, o->out, t);
tcg_temp_free_i64(t);
}
static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
@ -1612,8 +1576,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = false;
c.g1 = false;
c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_subi_i64(t, regs[r1], 1);
@ -1621,7 +1583,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
c.u.s32.a = tcg_temp_new_i32();
c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_temp_free_i64(t);
return help_branch(s, &c, is_imm, imm, o->in2);
}
@ -1635,8 +1596,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = false;
c.g1 = false;
c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, regs[r1], 32);
@ -1645,7 +1604,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
c.u.s32.a = tcg_temp_new_i32();
c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_temp_free_i64(t);
return help_branch(s, &c, 1, imm, o->in2);
}
@ -1659,8 +1617,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
c.cond = TCG_COND_NE;
c.is_64 = true;
c.g1 = true;
c.g2 = false;
tcg_gen_subi_i64(regs[r1], regs[r1], 1);
c.u.s64.a = regs[r1];
@ -1680,8 +1636,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
c.is_64 = false;
c.g1 = false;
c.g2 = false;
t = tcg_temp_new_i64();
tcg_gen_add_i64(t, regs[r1], regs[r3]);
@ -1690,7 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]);
store_reg32_i64(r1, t);
tcg_temp_free_i64(t);
return help_branch(s, &c, is_imm, imm, o->in2);
}
@ -1708,15 +1661,12 @@ static DisasJumpType op_bx64(DisasContext *s, DisasOps *o)
if (r1 == (r3 | 1)) {
c.u.s64.b = load_reg(r3 | 1);
c.g2 = false;
} else {
c.u.s64.b = regs[r3 | 1];
c.g2 = true;
}
tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
c.u.s64.a = regs[r1];
c.g1 = true;
return help_branch(s, &c, is_imm, imm, o->in2);
}
@ -1731,7 +1681,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps *o)
if (s->insn->data) {
c.cond = tcg_unsigned_cond(c.cond);
}
c.is_64 = c.g1 = c.g2 = true;
c.is_64 = true;
c.u.s64.a = o->in1;
c.u.s64.b = o->in2;
@ -2012,11 +1962,9 @@ static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]);
set_cc_static(s);
tcg_gen_extr_i128_i64(o->out, len, pair);
tcg_temp_free_i128(pair);
tcg_gen_add_i64(regs[r2], regs[r2], len);
tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
tcg_temp_free_i64(len);
return DISAS_NEXT;
}
@ -2118,7 +2066,6 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(t1, o->in1);
gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
set_cc_static(s);
tcg_temp_free_i32(t1);
return DISAS_NEXT;
}
@ -2128,7 +2075,6 @@ static DisasJumpType op_clst(DisasContext *s, DisasOps *o)
gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2);
tcg_gen_extr_i128_i64(o->in2, o->in1, pair);
tcg_temp_free_i128(pair);
set_cc_static(s);
return DISAS_NEXT;
@ -2140,7 +2086,6 @@ static DisasJumpType op_cps(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
tcg_gen_or_i64(o->out, o->out, t);
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@ -2156,14 +2101,12 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
addr = get_address(s, 0, b2, d2);
tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1,
get_mem_index(s), s->insn->data | MO_ALIGN);
tcg_temp_free_i64(addr);
/* Are the memory and expected values (un)equal? Note that this setcond
produces the output CC value, thus the NE sense of the test. */
cc = tcg_temp_new_i64();
tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out);
tcg_gen_extrl_i64_i32(cc_op, cc);
tcg_temp_free_i64(cc);
set_cc_static(s);
return DISAS_NEXT;
@ -2223,7 +2166,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE));
tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2,
get_mem_index(s), mop | MO_ALIGN);
tcg_temp_free_i64(addr);
/* Are the memory and expected values (un)equal? */
cc = tcg_temp_new_i64();
@ -2237,14 +2179,12 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
} else {
tcg_gen_mov_i64(o->out, old);
}
tcg_temp_free_i64(old);
/* If the comparison was equal, and the LSB of R2 was set,
then we need to flush the TLB (for all cpus). */
tcg_gen_xori_i64(cc, cc, 1);
tcg_gen_and_i64(cc, cc, o->in2);
tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab);
tcg_temp_free_i64(cc);
gen_helper_purge(cpu_env);
gen_set_label(lab);
@ -2259,9 +2199,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
TCGv_i32 t2 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t2, o->in1);
gen_helper_cvd(t1, t2);
tcg_temp_free_i32(t2);
tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@ -2363,7 +2301,6 @@ static DisasJumpType op_divs64(DisasContext *s, DisasOps *o)
gen_helper_divs64(t, cpu_env, o->in1, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
tcg_temp_free_i128(t);
return DISAS_NEXT;
}
@ -2373,7 +2310,6 @@ static DisasJumpType op_divu64(DisasContext *s, DisasOps *o)
gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
tcg_temp_free_i128(t);
return DISAS_NEXT;
}
@ -2428,8 +2364,6 @@ static DisasJumpType op_epsw(DisasContext *s, DisasOps *o)
if (r2 != 0) {
store_reg32_i64(r2, psw_mask);
}
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@ -2569,7 +2503,6 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
tcg_gen_movi_i64(tmp, ccm);
gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -2592,8 +2525,6 @@ static DisasJumpType op_ipm(DisasContext *s, DisasOps *o)
tcg_gen_extu_i32_i64(t2, cc_op);
tcg_gen_deposit_i64(t1, t1, t2, 4, 60);
tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return DISAS_NEXT;
}
@ -2925,21 +2856,17 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
if (c.is_64) {
tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
o->in2, o->in1);
free_compare(&c);
} else {
TCGv_i32 t32 = tcg_temp_new_i32();
TCGv_i64 t, z;
tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
free_compare(&c);
t = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t, t32);
tcg_temp_free_i32(t32);
z = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
tcg_temp_free_i64(t);
}
return DISAS_NEXT;
@ -2996,8 +2923,6 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
/* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
tcg_gen_shli_i64(t1, t1, 32);
gen_helper_load_psw(cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return DISAS_NORETURN;
}
@ -3014,8 +2939,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
gen_helper_load_psw(cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return DISAS_NORETURN;
}
#endif
@ -3040,7 +2963,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32_i64(r1, t1);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3055,8 +2977,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t2);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3069,9 +2989,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32_i64(r1, t1);
}
tcg_temp_free(t2);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3086,7 +3003,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32h_i64(r1, t1);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3101,8 +3017,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t2);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3115,9 +3029,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32h_i64(r1, t1);
}
tcg_temp_free(t2);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3141,11 +3052,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s));
tcg_gen_mov_i64(regs[r1], t1);
tcg_temp_free(t2);
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3157,8 +3066,6 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
tcg_gen_add_i64(o->in2, o->in2, t1);
tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
}
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -3180,8 +3087,6 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
a2 = get_address(s, 0, get_field(s, b2), get_field(s, d2));
tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN);
tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN);
tcg_temp_free_i64(a1);
tcg_temp_free_i64(a2);
/* ... and indicate that we performed them while interlocked. */
gen_op_movi_cc(s, 0);
@ -3253,9 +3158,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o)
static DisasJumpType op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
o->g_out = o->g_in2;
o->in2 = NULL;
o->g_in2 = false;
return DISAS_NEXT;
}
@ -3265,9 +3168,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
TCGv ar1 = tcg_temp_new_i64();
o->out = o->in2;
o->g_out = o->g_in2;
o->in2 = NULL;
o->g_in2 = false;
switch (s->base.tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
@ -3289,8 +3190,6 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
}
tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1]));
tcg_temp_free_i64(ar1);
return DISAS_NEXT;
}
@ -3298,11 +3197,8 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o)
{
o->out = o->in1;
o->out2 = o->in2;
o->g_out = o->g_in1;
o->g_out2 = o->g_in2;
o->in1 = NULL;
o->in2 = NULL;
o->g_in1 = o->g_in2 = false;
return DISAS_NEXT;
}
@ -3509,7 +3405,6 @@ static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@ -3517,7 +3412,6 @@ static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@ -3525,7 +3419,6 @@ static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@ -3533,7 +3426,6 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
}
@ -3544,7 +3436,6 @@ static DisasJumpType op_nabs(DisasContext *s, DisasOps *o)
tcg_gen_neg_i64(n, o->in2);
tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2);
tcg_temp_free_i64(n);
return DISAS_NEXT;
}
@ -3621,10 +3512,10 @@ static DisasJumpType op_ori(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
TCGv_i64 t = tcg_temp_new_i64();
assert(!o->g_in2);
tcg_gen_shli_i64(o->in2, o->in2, shift);
tcg_gen_or_i64(o->out, o->in1, o->in2);
tcg_gen_shli_i64(t, o->in2, shift);
tcg_gen_or_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
@ -3809,7 +3700,6 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
/* If this is a test-only form, arrange to discard the result. */
if (i3 & 0x80) {
o->out = tcg_temp_new_i64();
o->g_out = false;
}
i3 &= 63;
@ -3879,9 +3769,6 @@ static DisasJumpType op_rll32(DisasContext *s, DisasOps *o)
tcg_gen_extrl_i64_i32(t2, o->in2);
tcg_gen_rotl_i32(to, t1, t2);
tcg_gen_extu_i32_i64(o->out, to);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(to);
return DISAS_NEXT;
}
@ -4022,7 +3909,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
} else {
tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
}
free_compare(&c);
r1 = get_field(s, r1);
a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
@ -4037,12 +3923,10 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
h = tcg_temp_new_i64();
tcg_gen_shri_i64(h, regs[r1], 32);
tcg_gen_qemu_st32(h, a, get_mem_index(s));
tcg_temp_free_i64(h);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_i64(a);
gen_set_label(lab);
return DISAS_NEXT;
@ -4059,9 +3943,6 @@ static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
t = o->in1;
}
gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2);
if (s->insn->data == 31) {
tcg_temp_free_i64(t);
}
tcg_gen_shl_i64(o->out, o->in1, o->in2);
/* The arithmetic left shift is curious in that it does not affect
the sign bit. Copy that over from the source unchanged. */
@ -4128,8 +4009,6 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasOps *o)
tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3);
tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -4170,8 +4049,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
/* store second operand in GR1 */
tcg_gen_mov_i64(regs[1], o->in2);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -4231,9 +4108,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
tcg_temp_free_i64(c1);
tcg_temp_free_i64(c2);
tcg_temp_free_i64(todpr);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@ -4447,7 +4321,6 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, psw_mask, 56);
tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
tcg_temp_free_i64(t);
if (s->fields.op == 0xac) {
tcg_gen_andi_i64(psw_mask, psw_mask,
@ -4558,7 +4431,6 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
}
break;
}
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -4602,8 +4474,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
tcg_gen_add_i64(o->in2, o->in2, t4);
r1 = (r1 + 1) & 15;
}
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@ -4790,7 +4660,6 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o)
gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, pair);
tcg_temp_free_i128(pair);
set_cc_static(s);
return DISAS_NEXT;
}
@ -4836,7 +4705,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
}
gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes);
tcg_temp_free_i32(tst);
set_cc_static(s);
return DISAS_NEXT;
}
@ -4955,10 +4823,10 @@ static DisasJumpType op_xori(DisasContext *s, DisasOps *o)
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
uint64_t mask = ((1ull << size) - 1) << shift;
TCGv_i64 t = tcg_temp_new_i64();
assert(!o->g_in2);
tcg_gen_shli_i64(o->in2, o->in2, shift);
tcg_gen_xor_i64(o->out, o->in1, o->in2);
tcg_gen_shli_i64(t, o->in2, shift);
tcg_gen_xor_i64(o->out, o->in1, t);
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
@ -4989,15 +4857,14 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
static DisasJumpType op_zero(DisasContext *s, DisasOps *o)
{
o->out = tcg_const_i64(0);
o->out = tcg_constant_i64(0);
return DISAS_NEXT;
}
static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
{
o->out = tcg_const_i64(0);
o->out = tcg_constant_i64(0);
o->out2 = o->out;
o->g_out2 = true;
return DISAS_NEXT;
}
@ -5265,7 +5132,6 @@ static void prep_new_x(DisasContext *s, DisasOps *o)
static void prep_r1(DisasContext *s, DisasOps *o)
{
o->out = regs[get_field(s, r1)];
o->g_out = true;
}
#define SPEC_prep_r1 0
@ -5274,7 +5140,6 @@ static void prep_r1_P(DisasContext *s, DisasOps *o)
int r1 = get_field(s, r1);
o->out = regs[r1];
o->out2 = regs[r1 + 1];
o->g_out = o->g_out2 = true;
}
#define SPEC_prep_r1_P SPEC_r1_even
@ -5343,7 +5208,6 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o)
store_reg32_i64(r1 + 1, o->out);
tcg_gen_shri_i64(t, o->out, 32);
store_reg32_i64(r1, t);
tcg_temp_free_i64(t);
}
#define SPEC_wout_r1_D32 SPEC_r1_even
@ -5499,7 +5363,6 @@ static void in1_r1(DisasContext *s, DisasOps *o)
static void in1_r1_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r1)];
o->g_in1 = true;
}
#define SPEC_in1_r1_o 0
@ -5533,7 +5396,6 @@ static void in1_r1p1(DisasContext *s, DisasOps *o)
static void in1_r1p1_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r1) + 1];
o->g_in1 = true;
}
#define SPEC_in1_r1p1_o SPEC_r1_even
@ -5588,7 +5450,6 @@ static void in1_r3(DisasContext *s, DisasOps *o)
static void in1_r3_o(DisasContext *s, DisasOps *o)
{
o->in1 = regs[get_field(s, r3)];
o->g_in1 = true;
}
#define SPEC_in1_r3_o 0
@ -5719,7 +5580,6 @@ static void in1_m1_64(DisasContext *s, DisasOps *o)
static void in2_r1_o(DisasContext *s, DisasOps *o)
{
o->in2 = regs[get_field(s, r1)];
o->g_in2 = true;
}
#define SPEC_in2_r1_o 0
@ -5754,7 +5614,6 @@ static void in2_r2(DisasContext *s, DisasOps *o)
static void in2_r2_o(DisasContext *s, DisasOps *o)
{
o->in2 = regs[get_field(s, r2)];
o->g_in2 = true;
}
#define SPEC_in2_r2_o 0
@ -5903,7 +5762,7 @@ static void in2_sh(DisasContext *s, DisasOps *o)
int d2 = get_field(s, d2);
if (b2 == 0) {
o->in2 = tcg_const_i64(d2 & 0x3f);
o->in2 = tcg_constant_i64(d2 & 0x3f);
} else {
o->in2 = get_address(s, 0, b2, d2);
tcg_gen_andi_i64(o->in2, o->in2, 0x3f);
@ -6016,46 +5875,46 @@ static void in2_mri2_64(DisasContext *s, DisasOps *o)
static void in2_i2(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64(get_field(s, i2));
o->in2 = tcg_constant_i64(get_field(s, i2));
}
#define SPEC_in2_i2 0
static void in2_i2_8u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64((uint8_t)get_field(s, i2));
o->in2 = tcg_constant_i64((uint8_t)get_field(s, i2));
}
#define SPEC_in2_i2_8u 0
static void in2_i2_16u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64((uint16_t)get_field(s, i2));
o->in2 = tcg_constant_i64((uint16_t)get_field(s, i2));
}
#define SPEC_in2_i2_16u 0
static void in2_i2_32u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64((uint32_t)get_field(s, i2));
o->in2 = tcg_constant_i64((uint32_t)get_field(s, i2));
}
#define SPEC_in2_i2_32u 0
static void in2_i2_16u_shl(DisasContext *s, DisasOps *o)
{
uint64_t i2 = (uint16_t)get_field(s, i2);
o->in2 = tcg_const_i64(i2 << s->insn->data);
o->in2 = tcg_constant_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_16u_shl 0
static void in2_i2_32u_shl(DisasContext *s, DisasOps *o)
{
uint64_t i2 = (uint32_t)get_field(s, i2);
o->in2 = tcg_const_i64(i2 << s->insn->data);
o->in2 = tcg_constant_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_32u_shl 0
#ifndef CONFIG_USER_ONLY
static void in2_insn(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64(s->fields.raw_insn);
o->in2 = tcg_constant_i64(s->fields.raw_insn);
}
#define SPEC_in2_insn 0
#endif
@ -6481,31 +6340,6 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
}
/* Free any temporaries created by the helpers. */
if (o.out && !o.g_out) {
tcg_temp_free_i64(o.out);
}
if (o.out2 && !o.g_out2) {
tcg_temp_free_i64(o.out2);
}
if (o.in1 && !o.g_in1) {
tcg_temp_free_i64(o.in1);
}
if (o.in2 && !o.g_in2) {
tcg_temp_free_i64(o.in2);
}
if (o.addr1) {
tcg_temp_free_i64(o.addr1);
}
if (o.out_128) {
tcg_temp_free_i128(o.out_128);
}
if (o.in1_128) {
tcg_temp_free_i128(o.in1_128);
}
if (o.in2_128) {
tcg_temp_free_i128(o.in2_128);
}
/* io should be the last instruction in tb when icount is enabled */
if (unlikely(icount && ret == DISAS_NEXT)) {
ret = DISAS_TOO_MANY;

143
target/s390x/tcg/translate_vx.c.inc
View File

@ -183,8 +183,6 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
/* generate the final ptr by adding cpu_env */
tcg_gen_trunc_i64_ptr(ptr, tmp);
tcg_gen_add_ptr(ptr, ptr, cpu_env);
tcg_temp_free_i64(tmp);
}
#define gen_gvec_2(v1, v2, gen) \
@ -272,13 +270,6 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
fn(dl, dh, al, ah, bl, bh);
write_vec_element_i64(dh, d, 0, ES_64);
write_vec_element_i64(dl, d, 1, ES_64);
tcg_temp_free_i64(dh);
tcg_temp_free_i64(dl);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(al);
tcg_temp_free_i64(bh);
tcg_temp_free_i64(bl);
}
typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
@ -305,15 +296,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
fn(dl, dh, al, ah, bl, bh, cl, ch);
write_vec_element_i64(dh, d, 0, ES_64);
write_vec_element_i64(dl, d, 1, ES_64);
tcg_temp_free_i64(dh);
tcg_temp_free_i64(dl);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(al);
tcg_temp_free_i64(bh);
tcg_temp_free_i64(bl);
tcg_temp_free_i64(ch);
tcg_temp_free_i64(cl);
}
static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
@ -351,7 +333,6 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -386,7 +367,6 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
write_vec_element_i64(t, get_field(s, v1), 0, ES_64);
tcg_gen_movi_i64(t, generate_byte_mask(i2));
write_vec_element_i64(t, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(t);
}
return DISAS_NEXT;
}
@ -427,8 +407,6 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ);
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -451,7 +429,6 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
gen_gvec_dup_i64(es, get_field(s, v1), tmp);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -469,7 +446,6 @@ static DisasJumpType op_vlebr(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -486,7 +462,6 @@ static DisasJumpType op_vlbrrep(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
gen_gvec_dup_i64(es, get_field(s, v1), tmp);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -518,7 +493,6 @@ static DisasJumpType op_vllebrz(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
write_vec_element_i64(tcg_constant_i64(0), get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -572,9 +546,6 @@ static DisasJumpType op_vlbr(DisasContext *s, DisasOps *o)
write:
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -592,7 +563,6 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -647,8 +617,6 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -688,8 +656,6 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
tcg_temp_free_ptr(ptr);
return DISAS_NEXT;
}
@ -730,7 +696,6 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
gen_gvec_dup_imm(es, get_field(s, v1), 0);
write_vec_element_i64(t, get_field(s, v1), enr, es);
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
@ -768,9 +733,6 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
/* Store the last element, loaded first */
write_vec_element_i64(t0, v1, 1, ES_64);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@ -794,8 +756,6 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, bytes);
tcg_temp_free_i64(bytes);
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@ -835,8 +795,6 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
tcg_temp_free_ptr(ptr);
return DISAS_NEXT;
}
@ -856,7 +814,6 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@ -898,7 +855,6 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, v1, dst_idx, es);
}
}
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -974,7 +930,6 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(tmp, v1, dst_idx, dst_es);
}
tcg_temp_free_i64(tmp);
} else {
gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]);
}
@ -1004,8 +959,6 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
read_vec_element_i64(t1, get_field(s, v3), i3, ES_64);
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
@ -1057,7 +1010,6 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1098,7 +1050,6 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN);
write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1116,7 +1067,6 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1134,7 +1084,6 @@ static DisasJumpType op_vstebr(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1189,9 +1138,6 @@ write:
tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_LEUQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_LEUQ);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -1209,7 +1155,6 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
tmp = tcg_temp_new_i64();
read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1251,9 +1196,6 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
}
@ -1284,7 +1226,6 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
}
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
}
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1297,7 +1238,6 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
@ -1335,7 +1275,6 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
write_vec_element_i64(tmp, v1, dst_idx, dst_es);
}
}
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -1377,10 +1316,6 @@ static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
/* Isolate and shift the carry into position */
tcg_gen_and_i64(d, d, msb_mask);
tcg_gen_shri_i64(d, d, msb_bit_nr);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t3);
}
static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@ -1399,7 +1334,6 @@ static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_add_i32(t, a, b);
tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b);
tcg_temp_free_i32(t);
}
static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@ -1408,7 +1342,6 @@ static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
tcg_gen_add_i64(t, a, b);
tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
tcg_temp_free_i64(t);
}
static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
@ -1422,9 +1355,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
tcg_gen_mov_i64(dh, zero);
tcg_temp_free_i64(th);
tcg_temp_free_i64(tl);
}
static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
@ -1460,8 +1390,6 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_extract_i64(tl, cl, 0, 1);
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero);
tcg_temp_free_i64(tl);
}
static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
@ -1490,9 +1418,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
tcg_gen_mov_i64(dh, zero);
tcg_temp_free_i64(tl);
tcg_temp_free_i64(th);
}
static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
@ -1533,9 +1458,6 @@ static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_addi_i64(t0, t0, 1);
tcg_gen_shri_i64(t0, t0, 1);
tcg_gen_extrl_i64_i32(d, t0);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
@ -1550,10 +1472,6 @@ static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
gen_addi2_i64(dl, dh, dl, dh, 1);
tcg_gen_extract2_i64(dl, dl, dh, 1);
tcg_temp_free_i64(dh);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(bh);
}
static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
@ -1586,9 +1504,6 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
tcg_gen_addi_i64(t0, t0, 1);
tcg_gen_shri_i64(t0, t0, 1);
tcg_gen_extrl_i64_i32(d, t0);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
@ -1599,8 +1514,6 @@ static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
gen_addi2_i64(dl, dh, dl, dh, 1);
tcg_gen_extract2_i64(dl, dl, dh, 1);
tcg_temp_free_i64(dh);
}
static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
@ -1635,9 +1548,6 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
}
gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(sum);
return DISAS_NEXT;
}
@ -1682,9 +1592,6 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
read_vec_element_i64(high, get_field(s, v1), 0, ES_64);
read_vec_element_i64(low, get_field(s, v1), 1, ES_64);
gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
tcg_temp_free_i64(low);
tcg_temp_free_i64(high);
}
return DISAS_NEXT;
}
@ -1853,8 +1760,6 @@ static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i32(t0, a, b);
tcg_gen_add_i32(d, t0, c);
tcg_temp_free_i32(t0);
}
static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
@ -1869,10 +1774,6 @@ static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_add_i64(t0, t0, t2);
tcg_gen_extrh_i64_i32(d, t0);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
@ -1887,10 +1788,6 @@ static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_add_i64(t0, t0, t2);
tcg_gen_extrh_i64_i32(d, t0);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
@ -1974,7 +1871,6 @@ static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_muls2_i32(t, d, a, b);
tcg_temp_free_i32(t);
}
static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
@ -1982,7 +1878,6 @@ static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_mulu2_i32(t, d, a, b);
tcg_temp_free_i32(t);
}
static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
@ -2099,11 +1994,6 @@ static DisasJumpType op_vmsl(DisasContext *s, DisasOps *o)
/* Store final result into v1. */
write_vec_element_i64(h1, get_field(s, v1), 0, ES_64);
write_vec_element_i64(l1, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(l1);
tcg_temp_free_i64(h1);
tcg_temp_free_i64(l2);
tcg_temp_free_i64(h2);
return DISAS_NEXT;
}
@ -2169,8 +2059,6 @@ static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
tcg_gen_and_i32(t, t, b);
tcg_gen_andc_i32(d, d, b);
tcg_gen_or_i32(d, d, t);
tcg_temp_free_i32(t);
}
static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
@ -2181,8 +2069,6 @@ static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
tcg_gen_and_i64(t, t, b);
tcg_gen_andc_i64(d, d, b);
tcg_gen_or_i64(d, d, t);
tcg_temp_free_i64(t);
}
static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
@ -2291,7 +2177,6 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
default:
g_assert_not_reached();
}
tcg_temp_free_i32(shift);
}
return DISAS_NEXT;
}
@ -2311,7 +2196,6 @@ static DisasJumpType gen_vsh_by_byte(DisasContext *s, DisasOps *o,
read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
tcg_gen_andi_i64(shift, shift, byte ? 0x78 : 7);
gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), shift, 0, gen);
tcg_temp_free_i64(shift);
}
return DISAS_NEXT;
}
@ -2367,10 +2251,6 @@ static DisasJumpType op_vsld(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
return DISAS_NEXT;
}
@ -2397,10 +2277,6 @@ static DisasJumpType op_vsrd(DisasContext *s, DisasOps *o)
write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
return DISAS_NEXT;
}
@ -2445,9 +2321,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
/* "invert" the result: -1 -> 0; 0 -> 1 */
tcg_gen_addi_i64(dl, th, 1);
tcg_gen_mov_i64(dh, zero);
tcg_temp_free_i64(th);
tcg_temp_free_i64(tl);
}
static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
@ -2482,8 +2355,6 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_not_i64(tl, bl);
tcg_gen_not_i64(th, bh);
gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch);
tcg_temp_free_i64(tl);
tcg_temp_free_i64(th);
}
static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
@ -2508,9 +2379,6 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_not_i64(tl, bl);
tcg_gen_not_i64(th, bh);
gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch);
tcg_temp_free_i64(tl);
tcg_temp_free_i64(th);
}
static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
@ -2550,8 +2418,6 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64);
}
tcg_temp_free_i64(sum);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@ -2580,10 +2446,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
}
write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64);
write_vec_element_i64(suml, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(sumh);
tcg_temp_free_i64(suml);
tcg_temp_free_i64(tmpl);
return DISAS_NEXT;
}
@ -2611,8 +2473,6 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
}
write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32);
}
tcg_temp_free_i32(sum);
tcg_temp_free_i32(tmp);
return DISAS_NEXT;
}
@ -3399,9 +3259,6 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
read_vec_element_i64(tmp, v2, 1, ES_64);
write_vec_element_i64(tmp, v1, 1, ES_64);
}
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}

1
target/sh4/cpu-param.h
View File

@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define NB_MMU_MODES 2
#endif

35
target/sh4/translate.c
View File

@ -526,13 +526,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2);
TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
}
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
}
return;
@ -694,7 +694,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300e: /* addc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
@ -754,7 +754,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);
/* shift left arg1, saving the bit being pushed out and inserting
T on the right */
@ -849,7 +849,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x600a: /* negc Rm,Rn */
{
TCGv t0 = tcg_const_i32(0);
TCGv t0 = tcg_constant_i32(0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
REG(B7_4), t0, cpu_sr_t, t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
@ -913,7 +913,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300a: /* subc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
@ -1242,7 +1242,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv imm;
CHECK_NOT_DELAY_SLOT
gen_save_cpu_state(ctx, true);
imm = tcg_const_i32(B7_0);
imm = tcg_constant_i32(B7_0);
gen_helper_trapa(cpu_env, imm);
ctx->base.is_jmp = DISAS_NORETURN;
}
@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
return;
case 0x401b: /* tas.b @Rn */
{
TCGv val = tcg_const_i32(0x80);
tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
ctx->memidx, MO_UB);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
}
tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
tcg_constant_i32(0x80), ctx->memidx, MO_UB);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
@ -1712,8 +1709,8 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_1
{
TCGv m = tcg_const_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_fipr(cpu_env, m, n);
return;
}
@ -1725,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx)
if ((ctx->opcode & 0x0300) != 0x0100) {
goto do_illegal;
}
TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_ftrv(cpu_env, n);
return;
}
@ -1929,7 +1926,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
op_dst = B11_8;
op_opc = INDEX_op_xor_i32;
op_arg = tcg_const_i32(-1);
op_arg = tcg_constant_i32(-1);
break;
case 0x7000 ... 0x700f: /* add #imm,Rn */
@ -1937,7 +1934,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_opc = INDEX_op_add_i32;
op_arg = tcg_const_i32(B7_0s);
op_arg = tcg_constant_i32(B7_0s);
break;
case 0x3000: /* cmp/eq Rm,Rn */
@ -1983,7 +1980,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_opc = INDEX_op_setcond_i32;
op_arg = tcg_const_i32(0);
op_arg = tcg_constant_i32(0);
NEXT_INSN;
if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */

2
target/sparc/cpu-param.h
View File

@ -16,13 +16,11 @@
# else
# define TARGET_VIRT_ADDR_SPACE_BITS 44
# endif
# define NB_MMU_MODES 6
#else
# define TARGET_LONG_BITS 32
# define TARGET_PAGE_BITS 12 /* 4k */
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define NB_MMU_MODES 3
#endif
#endif

14
target/sparc/translate.c
View File

@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
int width, bool cc, bool left)
{
TCGv lo1, lo2, t1, t2;
TCGv lo1, lo2;
uint64_t amask, tabl, tabr;
int shift, imask, omask;
@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
tcg_gen_shli_tl(lo1, lo1, shift);
tcg_gen_shli_tl(lo2, lo2, shift);
t1 = tcg_const_tl(tabl);
t2 = tcg_const_tl(tabr);
tcg_gen_shr_tl(lo1, t1, lo1);
tcg_gen_shr_tl(lo2, t2, lo2);
tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
tcg_gen_andi_tl(dst, lo1, omask);
tcg_gen_andi_tl(lo2, lo2, omask);
@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
lo2 |= -(s1 == s2)
dst &= lo2
*/
tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
tcg_gen_neg_tl(t1, t1);
tcg_gen_or_tl(lo2, lo2, t1);
tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2);
tcg_gen_neg_tl(lo1, lo1);
tcg_gen_or_tl(lo2, lo2, lo1);
tcg_gen_and_tl(dst, dst, lo2);
}

1
target/tricore/cpu-param.h
View File

@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 14
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 3
#endif

476
target/tricore/translate.c
View File

File diff suppressed because it is too large Load Diff

1
target/xtensa/cpu-param.h
View File

@ -16,6 +16,5 @@
#else
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define NB_MMU_MODES 4
#endif

9
tcg/i386/tcg-target.c.inc
View File

@ -3651,6 +3651,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,
break;
case MO_64:
t1 = tcg_temp_new_vec(type);
if (imm <= 32) {
/*
* We can emulate a small sign extend by performing an arithmetic
@ -3659,24 +3660,22 @@ static void expand_vec_sari(TCGType type, unsigned vece,
* does not, so we have to bound the smaller shift -- we get the
* same result in the high half either way.
*/
t1 = tcg_temp_new_vec(type);
tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
tcg_gen_shri_vec(MO_64, v0, v1, imm);
vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
tcgv_vec_arg(v0), tcgv_vec_arg(v0),
tcgv_vec_arg(t1), 0xaa);
tcg_temp_free_vec(t1);
} else {
/* Otherwise we will need to use a compare vs 0 to produce
* the sign-extend, shift and merge.
*/
t1 = tcg_const_zeros_vec(type);
tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1,
tcg_constant_vec(type, MO_64, 0), v1);
tcg_gen_shri_vec(MO_64, v0, v1, imm);
tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
tcg_gen_or_vec(MO_64, v0, v0, t1);
tcg_temp_free_vec(t1);
}
tcg_temp_free_vec(t1);
break;
default:

1
tcg/tcg-op-gvec.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "tcg/tcg-gvec-desc.h"

35
tcg/tcg-op-vec.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "tcg-internal.h"
@ -228,32 +229,6 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
}
}
TCGv_vec tcg_const_zeros_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
tcg_gen_dupi_vec(MO_64, ret, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
tcg_gen_dupi_vec(MO_64, ret, -1);
return ret;
}
TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
{
TCGTemp *t = tcgv_vec_temp(m);
return tcg_const_zeros_vec(t->base_type);
}
TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
{
TCGTemp *t = tcgv_vec_temp(m);
return tcg_const_ones_vec(t->base_type);
}
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
TCGTemp *rt = tcgv_vec_temp(r);
@ -430,9 +405,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
TCGv_vec t = tcg_const_ones_vec_matching(r);
tcg_gen_xor_vec(0, r, a, t);
tcg_temp_free_vec(t);
tcg_gen_xor_vec(0, r, a, tcg_constant_vec_matching(r, 0, -1));
}
tcg_swap_vecop_list(hold_list);
}
@ -445,9 +418,7 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {
TCGv_vec t = tcg_const_zeros_vec_matching(r);
tcg_gen_sub_vec(vece, r, t, a);
tcg_temp_free_vec(t);
tcg_gen_sub_vec(vece, r, tcg_constant_vec_matching(r, vece, 0), a);
}
tcg_swap_vecop_list(hold_list);
}

13
tcg/tcg-op.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "exec/plugin-gen.h"
@ -1562,9 +1563,7 @@ void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (is_power_of_2(arg2)) {
tcg_gen_shli_i64(ret, arg1, ctz64(arg2));
} else {
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_mul_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
tcg_gen_mul_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@ -1961,9 +1960,7 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
tcg_temp_free_i32(t);
} else {
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_clz_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@ -2015,9 +2012,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_ctpop_i64(ret, t);
tcg_temp_free_i64(t);
} else {
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_ctz_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
tcg_gen_ctz_i64(ret, arg1, tcg_constant_i64(arg2));
}
}

17
tcg/tcg.c
View File

@ -60,6 +60,7 @@
#include "elf.h"
#include "exec/log.h"
#include "tcg/tcg-ldst.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg-internal.h"
#include "accel/tcg/perf.h"
@ -1444,22 +1445,6 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val)
return tcg_constant_vec(t->base_type, vece, val);
}
TCGv_i32 tcg_const_i32(int32_t val)
{
TCGv_i32 t0;
t0 = tcg_temp_new_i32();
tcg_gen_movi_i32(t0, val);
return t0;
}
TCGv_i64 tcg_const_i64(int64_t val)
{
TCGv_i64 t0;
t0 = tcg_temp_new_i64();
tcg_gen_movi_i64(t0, val);
return t0;
}
/* Return true if OP may appear in the opcode stream.
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)